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The role of SiN/GaN cap interface charge and GaN cap layer to achieve enhancement mode GaN MIS-HEMT operation

K. Ahmeda, B. Ubochi, M.H. Alqaysi, A. Al-Khalidi, E. Wasige, Karol Kalna Orcid Logo

Microelectronics Reliability, Volume: 115, Start page: 113965

Swansea University Author: Karol Kalna Orcid Logo

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DOI (Published version): 10.1016/j.microrel.2020.113965

Abstract

The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to mea...

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Published in: Microelectronics Reliability
ISSN: 0026-2714
Published: Elsevier BV 2020
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URI: https://cronfa.swan.ac.uk/Record/cronfa55553
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Abstract: The thickness increase of gallium nitride (GaN) cap layer from 2 nm to 35 nm to achieve an enhancement mode GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) with a threshold voltage (Vth) of +0.5 V is studied using TCAD simulations. The simulations are calibrated to measured I-V characteristics of the 1 μm gate length GaN MIS-HEMT with the 2 nm thick GaN cap. A good agreement at low and high drain voltages (VDS=1 V and 5 V) between simulations and measurements is achieved by using a quantum-corrected drift-diffusion transport model. The enhancement mode GaN MIS-HEMT with a GaN cap thickness of 35 nm achieves Vth = + 0.5 V thanks to positive interface traps occurring between the SiN passivation layer and the GaN cap as reported experimentally. The simulations indicate that a parasitic channel is created at the interface between the SiN layer and the 35 nm GaN cap. Our study also shows an increase in the breakdown voltage from 100 V to 870 V when a thickness of the GaN cap layer increases from 15 nm to 35 nm.
Keywords: GaN HEMT, Enhancement mode, Interface traps, Parasitic channel, Cap layer
College: Faculty of Science and Engineering
Start Page: 113965

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