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Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET

Mustafa H. Alqaysi, Antonio Martinez, Khaled Ahmeda, Brendan Ubochi, Karol Kalna Orcid Logo, Antonio Martinez Muniz

IET Power Electronics, Volume: 12, Issue: 11, Pages: 2731 - 2740

Swansea University Authors: Karol Kalna Orcid Logo, Antonio Martinez Muniz

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DOI (Published version): 10.1049/iet-pel.2018.5897

Abstract

The reliability of silicon carbide metal oxide semiconductor field-effect transistors remains a challenge in power applications and relates to the SiO 2 –SiC interface. The presence of unwanted interface traps/defects degrades the device performance. The impact of acceptor traps/defects on the perfo...

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Published in: IET Power Electronics
ISSN: 1755-4535 1755-4543
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa52363
first_indexed 2019-10-07T20:23:57Z
last_indexed 2019-10-07T20:23:57Z
id cronfa52363
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spelling 2019-10-07T14:50:23.3411120 v2 52363 2019-10-07 Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false cd433784251add853672979313f838ec Antonio Martinez Muniz Antonio Martinez Muniz true false 2019-10-07 ACEM The reliability of silicon carbide metal oxide semiconductor field-effect transistors remains a challenge in power applications and relates to the SiO 2 –SiC interface. The presence of unwanted interface traps/defects degrades the device performance. The impact of acceptor traps/defects on the performance of a 4H-SiC vertical Diffused Metal Oxide Semiconductor Field Effect Transistor (DMOSFET) with a breakdown voltage of 1700 V is investigated. - and - characteristics were simulated, using a drift-diffusion model coupled to Fourier heat equations, and are in a good agreement with experimental results. The presence of interface traps/defects were shown to produce degradation of threshold voltage, but the impact diminishes as temperature increases. A threshold voltage shift of 3.5 V occurs for a trap concentration of 2 × 10 13  cm– 2 /eV at room temperature. The transfer characteristics obtained from electro-thermal modelling show a larger degradation than those at a constant temperature. This degradation increases with the drain bias increase. The threshold voltage from the electro-thermal simulations is 5 V compared to 4 V observed in constant 423 K temperature simulations at. Finally, the interface traps/defects increases breakdown voltage exhibiting a strong dependency on the trap density and their energy decay characteristics. Journal Article IET Power Electronics 12 11 2731 2740 1755-4535 1755-4543 31 12 2019 2019-12-31 10.1049/iet-pel.2018.5897 COLLEGE NANME Aerospace, Civil, Electrical, and Mechanical Engineering COLLEGE CODE ACEM Swansea University 2019-10-07T14:50:23.3411120 2019-10-07T14:38:55.8688854 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Mustafa H. Alqaysi 1 Antonio Martinez 2 Khaled Ahmeda 3 Brendan Ubochi 4 Karol Kalna 0000-0002-6333-9189 5 Antonio Martinez Muniz 6
title Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET
spellingShingle Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET
Karol Kalna
Antonio Martinez Muniz
title_short Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET
title_full Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET
title_fullStr Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET
title_full_unstemmed Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET
title_sort Impact of interface traps/defects and self-heating on the degradation of performance of a 4H-SiC VDMOSFET
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
cd433784251add853672979313f838ec
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
cd433784251add853672979313f838ec_***_Antonio Martinez Muniz
author Karol Kalna
Antonio Martinez Muniz
author2 Mustafa H. Alqaysi
Antonio Martinez
Khaled Ahmeda
Brendan Ubochi
Karol Kalna
Antonio Martinez Muniz
format Journal article
container_title IET Power Electronics
container_volume 12
container_issue 11
container_start_page 2731
publishDate 2019
institution Swansea University
issn 1755-4535
1755-4543
doi_str_mv 10.1049/iet-pel.2018.5897
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 0
active_str 0
description The reliability of silicon carbide metal oxide semiconductor field-effect transistors remains a challenge in power applications and relates to the SiO 2 –SiC interface. The presence of unwanted interface traps/defects degrades the device performance. The impact of acceptor traps/defects on the performance of a 4H-SiC vertical Diffused Metal Oxide Semiconductor Field Effect Transistor (DMOSFET) with a breakdown voltage of 1700 V is investigated. - and - characteristics were simulated, using a drift-diffusion model coupled to Fourier heat equations, and are in a good agreement with experimental results. The presence of interface traps/defects were shown to produce degradation of threshold voltage, but the impact diminishes as temperature increases. A threshold voltage shift of 3.5 V occurs for a trap concentration of 2 × 10 13  cm– 2 /eV at room temperature. The transfer characteristics obtained from electro-thermal modelling show a larger degradation than those at a constant temperature. This degradation increases with the drain bias increase. The threshold voltage from the electro-thermal simulations is 5 V compared to 4 V observed in constant 423 K temperature simulations at. Finally, the interface traps/defects increases breakdown voltage exhibiting a strong dependency on the trap density and their energy decay characteristics.
published_date 2019-12-31T06:03:29Z
_version_ 1851281280133496832
score 11.090362

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