Journal article 519 views 293 downloads
Influence of temperature and dimension in a 4H-SiC vertical power MOSFET
,
B Ubochi,
Stephen Batcup,
K Ahmeda
Engineering Research Express, Volume: 2, Issue: 4, Start page: 045020
Swansea University Authors:
MUSTAFA ALQAYSI, Antonio Martinez Muniz , Stephen Batcup
-
PDF | Version of Record
© 2020 The Author(s). Released under the terms of the Creative Commons Attribution 4.0 license
Download (3.16MB)
DOI (Published version): 10.1088/2631-8695/abc52b
Abstract
A study of the impact of dimension and temperature on a state of the art 4H-SiC power vertical DMOSFET has been carried out using drift-diffusion calculations in conjunction with electrical characterizations to extract physical parameters and doping profiles in a 6 μm channel length device. The mode...
| Published in: | Engineering Research Express |
|---|---|
| ISSN: | 2631-8695 |
| Published: |
IOP Publishing
2020
|
| Online Access: |
Check full text
|
| URI: | https://cronfa.swan.ac.uk/Record/cronfa55865 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Abstract: |
A study of the impact of dimension and temperature on a state of the art 4H-SiC power vertical DMOSFET has been carried out using drift-diffusion calculations in conjunction with electrical characterizations to extract physical parameters and doping profiles in a 6 μm channel length device. The model presented in this paper includes the effect of trapping in the channel/oxide interface. Using these parameters, the performance of corresponding lateral and vertical scaled devices are studied. Electrothermal simulations showing self-heating effects are also carried out. The results are qualitatively discussed with the help of an analytical physical model, which considers the interplay between the different device resistances. At low drain bias, the drain current is increased by 42.86% (ID = 5 A at VG = 20 V) when reducing the dimension vertically, whereas it is decreased by 28.57% (ID = 2.5 A at VG = 20 V) when reducing the dimension laterally. These effects are enhanced at high drain bias. In addition, the effect of dimension reduction for breakdown voltage, electric field and impact ionization is investigated. A substantial reduction in breakdown voltage was found when the vertical dimensions were decreased as compared to the lateral dimensions. |
|---|---|
| Keywords: |
SiC, DMOSFET, power devices, device modelling, 4H-SiC VDMOSFET |
| College: |
Faculty of Science and Engineering |
| Issue: |
4 |
| Start Page: |
045020 |