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SiC/Al4SiC4-Based Heterostructure Transistors
ACS Applied Electronic Materials, Volume: 2, Issue: 9, Pages: 3001 - 3007
Swansea University Author: Karol Kalna
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DOI (Published version): 10.1021/acsaelm.0c00614
Abstract
A wide-band-gap (WBG) SiC/Al4SiC4 heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al4SiC4, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and...
Published in: | ACS Applied Electronic Materials |
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ISSN: | 2637-6113 2637-6113 |
Published: |
American Chemical Society (ACS)
2020
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Online Access: |
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URI: | https://cronfa.swan.ac.uk/Record/cronfa55561 |
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Abstract: |
A wide-band-gap (WBG) SiC/Al4SiC4 heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al4SiC4, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and experimental data. The 5 μm gate length transistor is then laterally scaled to 2 and 1 μm gate length devices. The 5 μm gate length SiC/Al4SiC4 heterostructure transistor delivers a maximum drain current of 168 mA/mm, which increases to 244 mA/mm and 350 mA/mm for gate lengths of 2 and 1 μm, respectively. The device breakdown voltage is 59.0 V, which reduces to 31.0 V and to 18.0 V in the scaled 2 μm and the 1 μm gate length transistors, respectively. The scaled down 1 μm gate length device switches faster thanks to a higher transconductance of 65.1 mS/mm compared to only 1.69 mS/mm for the 5 μm gate length device. Finally, the subthreshold slope of the scaled devices is 197.3, 97.6, and 96.1 mV/dec for gate lengths of 5, 2, and 1 μm, respectively. |
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Keywords: |
heterostructure; ternary carbide; Al4SiC4; silvaco; transconductance; breakdown; HEMT |
College: |
Faculty of Science and Engineering |
Issue: |
9 |
Start Page: |
3001 |
End Page: |
3007 |