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SiC/Al4SiC4-Based Heterostructure Transistors

Simon Forster, Didier Chaussende, Karol Kalna Orcid Logo

ACS Applied Electronic Materials, Volume: 2, Issue: 9, Pages: 3001 - 3007

Swansea University Author: Karol Kalna Orcid Logo

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DOI (Published version): 10.1021/acsaelm.0c00614

Abstract

A wide-band-gap (WBG) SiC/Al4SiC4 heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al4SiC4, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and...

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Published in: ACS Applied Electronic Materials
ISSN: 2637-6113 2637-6113
Published: American Chemical Society (ACS) 2020
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URI: https://cronfa.swan.ac.uk/Record/cronfa55561
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first_indexed 2020-10-30T09:00:41Z
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spelling 2021-12-02T11:42:23.0185530 v2 55561 2020-10-30 SiC/Al4SiC4-Based Heterostructure Transistors 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2020-10-30 EEEG A wide-band-gap (WBG) SiC/Al4SiC4 heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al4SiC4, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and experimental data. The 5 μm gate length transistor is then laterally scaled to 2 and 1 μm gate length devices. The 5 μm gate length SiC/Al4SiC4 heterostructure transistor delivers a maximum drain current of 168 mA/mm, which increases to 244 mA/mm and 350 mA/mm for gate lengths of 2 and 1 μm, respectively. The device breakdown voltage is 59.0 V, which reduces to 31.0 V and to 18.0 V in the scaled 2 μm and the 1 μm gate length transistors, respectively. The scaled down 1 μm gate length device switches faster thanks to a higher transconductance of 65.1 mS/mm compared to only 1.69 mS/mm for the 5 μm gate length device. Finally, the subthreshold slope of the scaled devices is 197.3, 97.6, and 96.1 mV/dec for gate lengths of 5, 2, and 1 μm, respectively. Journal Article ACS Applied Electronic Materials 2 9 3001 3007 American Chemical Society (ACS) 2637-6113 2637-6113 heterostructure; ternary carbide; Al4SiC4; silvaco; transconductance; breakdown; HEMT 22 9 2020 2020-09-22 10.1021/acsaelm.0c00614 https://pubs.acs.org/doi/abs/10.1021/acsaelm.0c00614 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2021-12-02T11:42:23.0185530 2020-10-30T08:58:12.1222670 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Simon Forster 1 Didier Chaussende 2 Karol Kalna 0000-0002-6333-9189 3 55561__18563__b34422a9bbfe458fadd6cb00412396de.pdf 55561.pdf 2020-11-02T11:29:04.9032938 Output 513188 application/pdf Accepted Manuscript true 2021-08-26T00:00:00.0000000 true eng
title SiC/Al4SiC4-Based Heterostructure Transistors
spellingShingle SiC/Al4SiC4-Based Heterostructure Transistors
Karol Kalna
title_short SiC/Al4SiC4-Based Heterostructure Transistors
title_full SiC/Al4SiC4-Based Heterostructure Transistors
title_fullStr SiC/Al4SiC4-Based Heterostructure Transistors
title_full_unstemmed SiC/Al4SiC4-Based Heterostructure Transistors
title_sort SiC/Al4SiC4-Based Heterostructure Transistors
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Karol Kalna
author2 Simon Forster
Didier Chaussende
Karol Kalna
format Journal article
container_title ACS Applied Electronic Materials
container_volume 2
container_issue 9
container_start_page 3001
publishDate 2020
institution Swansea University
issn 2637-6113
2637-6113
doi_str_mv 10.1021/acsaelm.0c00614
publisher American Chemical Society (ACS)
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
url https://pubs.acs.org/doi/abs/10.1021/acsaelm.0c00614
document_store_str 1
active_str 0
description A wide-band-gap (WBG) SiC/Al4SiC4 heterostructure transistor with a gate length of 5 μm is designed using a ternary carbide of Al4SiC4, and its performance is simulated by Silvaco Atlas. The simulations use a mixture of parameters obtained from ensemble Monte Carlo simulations, DFT calculations, and experimental data. The 5 μm gate length transistor is then laterally scaled to 2 and 1 μm gate length devices. The 5 μm gate length SiC/Al4SiC4 heterostructure transistor delivers a maximum drain current of 168 mA/mm, which increases to 244 mA/mm and 350 mA/mm for gate lengths of 2 and 1 μm, respectively. The device breakdown voltage is 59.0 V, which reduces to 31.0 V and to 18.0 V in the scaled 2 μm and the 1 μm gate length transistors, respectively. The scaled down 1 μm gate length device switches faster thanks to a higher transconductance of 65.1 mS/mm compared to only 1.69 mS/mm for the 5 μm gate length device. Finally, the subthreshold slope of the scaled devices is 197.3, 97.6, and 96.1 mV/dec for gate lengths of 5, 2, and 1 μm, respectively.
published_date 2020-09-22T04:09:52Z
_version_ 1763753687616847872
score 11.037319

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