No Cover Image

Journal article 1312 views

A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability

Fan Li Orcid Logo, Qiu Song Orcid Logo, Amador Perez-Tomas Orcid Logo, Vishal Shah, Yogesh Sharma, Dean Hamilton Orcid Logo, Craig Fisher, Peter Gammon Orcid Logo, Mike Jennings Orcid Logo, Phil Mawby

IEEE Transactions on Electron Devices, Volume: 67, Issue: 1, Pages: 237 - 242

Swansea University Author: Mike Jennings Orcid Logo

Full text not available from this repository: check for access using links below.

Abstract

Despite the recent advances in 3C-SiC technology, there is a lack of statistical analysis on the reliability of SiO 2 layers on 3C-SiC, which is crucial in power MOS device developments. This article presents a comprehensive study of the medium- and long-term time-dependent dielectric breakdowns (TD...

Full description

Published in: IEEE Transactions on Electron Devices
ISSN: 0018-9383 1557-9646
Published: Institute of Electrical and Electronics Engineers (IEEE) 2020
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa53335
first_indexed 2020-01-23T13:57:35Z
last_indexed 2025-04-17T04:00:33Z
id cronfa53335
recordtype SURis
fullrecord <?xml version="1.0"?><rfc1807><datestamp>2025-04-16T14:21:19.4493337</datestamp><bib-version>v2</bib-version><id>53335</id><entry>2020-01-23</entry><title>A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability</title><swanseaauthors><author><sid>e0ba5d7ece08cd70c9f8f8683996454a</sid><ORCID>0000-0003-3270-0805</ORCID><firstname>Mike</firstname><surname>Jennings</surname><name>Mike Jennings</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2020-01-23</date><deptcode>ACEM</deptcode><abstract>Despite the recent advances in 3C-SiC technology, there is a lack of statistical analysis on the reliability of SiO 2 layers on 3C-SiC, which is crucial in power MOS device developments. This article presents a comprehensive study of the medium- and long-term time-dependent dielectric breakdowns (TDDBs) of 65-nm-thick SiO 2 layers thermally grown on a state-of-the-art 3C-SiC/Si wafer. Fowler&#x2013;Nordheim (F-N) tunneling is observed above 7 MV/cm and an effective barrier height of 3.7 eV is obtained, which is the highest known for native SiO 2 layers grown on the semiconductor substrate. The observed dependence of the oxide reliability on the gate active area suggests that the oxide quality has not reached the intrinsic level. Three failure mechanisms were identified and confirmed by both medium- and long-term results. Although two of them are likely due to extrinsic defects from material quality and fabrication steps, the one dominating the high field (&gt;8.5 MV/cm) should be attributed to the electron impact ionization within SiO 2 . At room temperature, the field acceleration factor is found to be $\approx 0.906$ dec/(MV/cm) for high fields, and the projected lifetime exceeds 10 years at 4.5 MV/cm.</abstract><type>Journal Article</type><journal>IEEE Transactions on Electron Devices</journal><volume>67</volume><journalNumber>1</journalNumber><paginationStart>237</paginationStart><paginationEnd>242</paginationEnd><publisher>Institute of Electrical and Electronics Engineers (IEEE)</publisher><placeOfPublication/><isbnPrint/><isbnElectronic/><issnPrint>0018-9383</issnPrint><issnElectronic>1557-9646</issnElectronic><keywords>Logic gates, Silicon, Reliability, Dielectrics, MOSFET, Annealing, Substrates, 3C-SiC, failure mechanism, MOS capacitor, reliability, time-dependent dielectric breakdown (TDDB)</keywords><publishedDay>1</publishedDay><publishedMonth>1</publishedMonth><publishedYear>2020</publishedYear><publishedDate>2020-01-01</publishedDate><doi>10.1109/ted.2019.2954911</doi><url/><notes/><college>COLLEGE NANME</college><department>Aerospace, Civil, Electrical, and Mechanical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>ACEM</DepartmentCode><institution>Swansea University</institution><apcterm>Not Required</apcterm><funders>H2020 Leadership in Enabling and Industrial Technologies (Grant Number: ID 720827)</funders><projectreference/><lastEdited>2025-04-16T14:21:19.4493337</lastEdited><Created>2020-01-23T09:49:53.1623697</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Fan</firstname><surname>Li</surname><orcid>0000-0002-9486-8876</orcid><order>1</order></author><author><firstname>Qiu</firstname><surname>Song</surname><orcid>0000-0001-9035-5611</orcid><order>2</order></author><author><firstname>Amador</firstname><surname>Perez-Tomas</surname><orcid>0000-0002-0551-3142</orcid><order>3</order></author><author><firstname>Vishal</firstname><surname>Shah</surname><order>4</order></author><author><firstname>Yogesh</firstname><surname>Sharma</surname><order>5</order></author><author><firstname>Dean</firstname><surname>Hamilton</surname><orcid>0000-0002-4797-8554</orcid><order>6</order></author><author><firstname>Craig</firstname><surname>Fisher</surname><order>7</order></author><author><firstname>Peter</firstname><surname>Gammon</surname><orcid>0000-0002-8819-3796</orcid><order>8</order></author><author><firstname>Mike</firstname><surname>Jennings</surname><orcid>0000-0003-3270-0805</orcid><order>9</order></author><author><firstname>Phil</firstname><surname>Mawby</surname><order>10</order></author></authors><documents/><OutputDurs/></rfc1807>
spelling 2025-04-16T14:21:19.4493337 v2 53335 2020-01-23 A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability e0ba5d7ece08cd70c9f8f8683996454a 0000-0003-3270-0805 Mike Jennings Mike Jennings true false 2020-01-23 ACEM Despite the recent advances in 3C-SiC technology, there is a lack of statistical analysis on the reliability of SiO 2 layers on 3C-SiC, which is crucial in power MOS device developments. This article presents a comprehensive study of the medium- and long-term time-dependent dielectric breakdowns (TDDBs) of 65-nm-thick SiO 2 layers thermally grown on a state-of-the-art 3C-SiC/Si wafer. Fowler–Nordheim (F-N) tunneling is observed above 7 MV/cm and an effective barrier height of 3.7 eV is obtained, which is the highest known for native SiO 2 layers grown on the semiconductor substrate. The observed dependence of the oxide reliability on the gate active area suggests that the oxide quality has not reached the intrinsic level. Three failure mechanisms were identified and confirmed by both medium- and long-term results. Although two of them are likely due to extrinsic defects from material quality and fabrication steps, the one dominating the high field (>8.5 MV/cm) should be attributed to the electron impact ionization within SiO 2 . At room temperature, the field acceleration factor is found to be $\approx 0.906$ dec/(MV/cm) for high fields, and the projected lifetime exceeds 10 years at 4.5 MV/cm. Journal Article IEEE Transactions on Electron Devices 67 1 237 242 Institute of Electrical and Electronics Engineers (IEEE) 0018-9383 1557-9646 Logic gates, Silicon, Reliability, Dielectrics, MOSFET, Annealing, Substrates, 3C-SiC, failure mechanism, MOS capacitor, reliability, time-dependent dielectric breakdown (TDDB) 1 1 2020 2020-01-01 10.1109/ted.2019.2954911 COLLEGE NANME Aerospace, Civil, Electrical, and Mechanical Engineering COLLEGE CODE ACEM Swansea University Not Required H2020 Leadership in Enabling and Industrial Technologies (Grant Number: ID 720827) 2025-04-16T14:21:19.4493337 2020-01-23T09:49:53.1623697 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Fan Li 0000-0002-9486-8876 1 Qiu Song 0000-0001-9035-5611 2 Amador Perez-Tomas 0000-0002-0551-3142 3 Vishal Shah 4 Yogesh Sharma 5 Dean Hamilton 0000-0002-4797-8554 6 Craig Fisher 7 Peter Gammon 0000-0002-8819-3796 8 Mike Jennings 0000-0003-3270-0805 9 Phil Mawby 10
title A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability
spellingShingle A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability
Mike Jennings
title_short A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability
title_full A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability
title_fullStr A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability
title_full_unstemmed A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability
title_sort A First Evaluation of Thick Oxide 3C-SiC MOS Capacitors Reliability
author_id_str_mv e0ba5d7ece08cd70c9f8f8683996454a
author_id_fullname_str_mv e0ba5d7ece08cd70c9f8f8683996454a_***_Mike Jennings
author Mike Jennings
author2 Fan Li
Qiu Song
Amador Perez-Tomas
Vishal Shah
Yogesh Sharma
Dean Hamilton
Craig Fisher
Peter Gammon
Mike Jennings
Phil Mawby
format Journal article
container_title IEEE Transactions on Electron Devices
container_volume 67
container_issue 1
container_start_page 237
publishDate 2020
institution Swansea University
issn 0018-9383
1557-9646
doi_str_mv 10.1109/ted.2019.2954911
publisher Institute of Electrical and Electronics Engineers (IEEE)
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 0
active_str 0
description Despite the recent advances in 3C-SiC technology, there is a lack of statistical analysis on the reliability of SiO 2 layers on 3C-SiC, which is crucial in power MOS device developments. This article presents a comprehensive study of the medium- and long-term time-dependent dielectric breakdowns (TDDBs) of 65-nm-thick SiO 2 layers thermally grown on a state-of-the-art 3C-SiC/Si wafer. Fowler–Nordheim (F-N) tunneling is observed above 7 MV/cm and an effective barrier height of 3.7 eV is obtained, which is the highest known for native SiO 2 layers grown on the semiconductor substrate. The observed dependence of the oxide reliability on the gate active area suggests that the oxide quality has not reached the intrinsic level. Three failure mechanisms were identified and confirmed by both medium- and long-term results. Although two of them are likely due to extrinsic defects from material quality and fabrication steps, the one dominating the high field (>8.5 MV/cm) should be attributed to the electron impact ionization within SiO 2 . At room temperature, the field acceleration factor is found to be $\approx 0.906$ dec/(MV/cm) for high fields, and the projected lifetime exceeds 10 years at 4.5 MV/cm.
published_date 2020-01-01T04:54:28Z
_version_ 1836505857908539392
score 11.380731