Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations

Adenekan, Olujide A.

doi:10.23889/Suthesis.50915

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Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations / Olujide A. Adenekan

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DOI (Published version): 10.23889/Suthesis.50915

Abstract

A design, optimisation, and scaling of a complementary metal-oxide-semiconductor CMOS-compatible lateral super-junction (SJ) multi-gate (MG) MOSFET(SJ-MGFET) based on silicon-on-insulator (SOI) technology is examined as a pre-ferred solution in mitigating the predominance of channel resistance durin...

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Published:	2019
Institution:	Swansea University
Degree level:	Doctoral
Degree name:	Ph.D
URI:	https://cronfa.swan.ac.uk/Record/cronfa50915

first_indexed	2019-06-24T20:54:08Z
last_indexed	2019-06-25T18:19:48Z
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fullrecord	<?xml version="1.0"?><rfc1807><datestamp>2019-06-25T11:15:52.0114859</datestamp><bib-version>v2</bib-version><id>50915</id><entry>2019-06-24</entry><title>Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations</title><swanseaauthors/><date>2019-06-24</date><abstract>A design, optimisation, and scaling of a complementary metal-oxide-semiconductor CMOS-compatible lateral super-junction (SJ) multi-gate (MG) MOSFET(SJ-MGFET) based on silicon-on-insulator (SOI) technology is examined as a pre-ferred solution in mitigating the predominance of channel resistance during operation at a low voltage. In order to overcome the preponderance of the channel resistance, the SJ-MGFET uses a non-planar 3-D embedded trench gate and a folded alternat-ing U-shaped n/p– SJ drift region pillar. The trench gate will redistribute electron current crowding near the top surface of the n− pillar reducing the channel resis-tance. The folded U-shaped n/p– pillar uniformly distributes the electric ﬁeld in the SJ drift region.The variations in the device architecture of a 1 µm gate length lateral super-junction (SJ) multi-gate MOSFET (SJ-MGFET) are explored using the physically based commercial 3-D TCAD device simulations by Silvaco. Investigation and analysis of diﬀerent carrier transport models are carried out with diﬀerent doping proﬁles by calibrating the drift-diﬀusion simulations to experimental I-V characteristics and breakdown voltage of the SJ-MGFET. The study, then aimed to improve drive current, breakdown voltage (BV ), and speciﬁc on-resistance (Ron,sp). The eﬀect of charge imbalance in the SJ pillar unit on the device breakdown voltage is studied with variations in the drift region length. It is observed that the charge imbalance in the SJ unit barely changes due to the ﬁxed ratio between the pillar width and the pillar height.It has been reported that the simulated and optimised SJ-MGFET device achieves 41% increase in the drive current with an on-oﬀ ratio of 5×106 at a drain voltage of 10 V and a gate voltage of 20 V , thereby demonstrating a big advantage of the multi-gate device design to reduce the leakage current. The results have shown that the optimised 1 µm gate length SJ-MGFET device oﬀers a speciﬁc on-resistance of 0.21 mΩ.cm2 and a breakdown voltage of 65 V with a trench-gate depth of 2.7 µm, a pillar height of 3.6 µm and a drift region length of 3.5 µm. In addition, it achieves 68%, 52% and 15% reduction in the speciﬁc on-resistance compared to the reported fabricated SJ-LDMOSFET, fabricated SJ-FinFET and simulated SJ-FinFET at the same BV rating, thereby capable of oﬀering a better performance in terms of a high drive current, a maximum breakdown voltage, a minimum speciﬁc on-resistance, and excellent FoM for sub - 100 V rating applications.Furthermore, the potentiality of scaling the device architecture of the optimised SJ-MGFET is examined from the 1 µm gate length to 0.5 µm, and 0.25 µm, respectively. Diﬀerent scaling approaches is carefully explored in all dimensions of the 3-D device structure in the simulations. The scaling down of the 1.0 µm gate length SJ-MGFET structure laterally (along the y-axis) by scaling the channel length, the gate length, the gate oxide thickness, and the SJ drift unit length by a factor S to shrink the gate length of 1.0 µm to 0.5 µm and 0.25 µm is examined in the simulations in this thesis. In order to prevent a weak electrostatic integrity in the scaled 0.5 µm and 0.25 µm gate lengths (Lgate) SJ-MGFETs, the doping proﬁle is optimised aiming at achieving a maximum drive current, a minimum leakage current, a high switching capability, a low speciﬁc on-resistance, and an improve avalanche capabilities of the devices. The scaled and optimised SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm achieve 30% and 63% increase in the drive current in comparison with the 1.0 µm gate length SJ-MGFET at a drain voltage of 0.1 V and a gate voltage of 15 V . Additionally, the scaled SJ-MGFETs oﬀer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V with a gate length of 0.5 µm and 0.25 µm, respectively. The SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm having a pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low speciﬁc on-resistance (Ron,sp) of 7.68 mΩ.mm2 and 2.24 mΩ.mm2 (VGS = 10 V ) and breakdown voltage (BV ) of 48 V and 26 V , respectively.Finally, the lateral scaling and optimisation of the 1 µm gate length SJ-MGFET to gate lengths of 0.5 µm and 0.25 µm using Silvaco Technology Computer Aided Design (TCAD) simulations has shown that the FoM of the non-planar transistor can be greatly improved in terms of switching speed, drive current, breakdown voltage, speciﬁc on-resistance, and physical density for a higher integration in a CMOS architecture.</abstract><type>E-Thesis</type><journal/><publisher/><keywords/><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2019</publishedYear><publishedDate>2019-12-31</publishedDate><doi>10.23889/Suthesis.50915</doi><url/><notes/><college>COLLEGE NANME</college><CollegeCode>COLLEGE CODE</CollegeCode><institution>Swansea University</institution><degreelevel>Doctoral</degreelevel><degreename>Ph.D</degreename><apcterm/><lastEdited>2019-06-25T11:15:52.0114859</lastEdited><Created>2019-06-24T16:55:41.4899757</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Engineering and Applied Sciences - Uncategorised</level></path><authors><author><firstname>Olujide A.</firstname><surname>Adenekan</surname><order>1</order></author></authors><documents><document><filename>0050915-25062019110536.pdf</filename><originalFilename>Adenekan_Olujide_A_PhD_Thesis_Final.pdf</originalFilename><uploaded>2019-06-25T11:05:36.6870000</uploaded><type>Output</type><contentLength>6268875</contentLength><contentType>application/pdf</contentType><version>E-Thesis – open access</version><cronfaStatus>true</cronfaStatus><embargoDate>2019-06-24T00:00:00.0000000</embargoDate><copyrightCorrect>true</copyrightCorrect></document></documents><OutputDurs/></rfc1807>
spelling	2019-06-25T11:15:52.0114859 v2 50915 2019-06-24 Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations 2019-06-24 A design, optimisation, and scaling of a complementary metal-oxide-semiconductor CMOS-compatible lateral super-junction (SJ) multi-gate (MG) MOSFET(SJ-MGFET) based on silicon-on-insulator (SOI) technology is examined as a pre-ferred solution in mitigating the predominance of channel resistance during operation at a low voltage. In order to overcome the preponderance of the channel resistance, the SJ-MGFET uses a non-planar 3-D embedded trench gate and a folded alternat-ing U-shaped n/p– SJ drift region pillar. The trench gate will redistribute electron current crowding near the top surface of the n− pillar reducing the channel resis-tance. The folded U-shaped n/p– pillar uniformly distributes the electric ﬁeld in the SJ drift region.The variations in the device architecture of a 1 µm gate length lateral super-junction (SJ) multi-gate MOSFET (SJ-MGFET) are explored using the physically based commercial 3-D TCAD device simulations by Silvaco. Investigation and analysis of diﬀerent carrier transport models are carried out with diﬀerent doping proﬁles by calibrating the drift-diﬀusion simulations to experimental I-V characteristics and breakdown voltage of the SJ-MGFET. The study, then aimed to improve drive current, breakdown voltage (BV ), and speciﬁc on-resistance (Ron,sp). The eﬀect of charge imbalance in the SJ pillar unit on the device breakdown voltage is studied with variations in the drift region length. It is observed that the charge imbalance in the SJ unit barely changes due to the ﬁxed ratio between the pillar width and the pillar height.It has been reported that the simulated and optimised SJ-MGFET device achieves 41% increase in the drive current with an on-oﬀ ratio of 5×106 at a drain voltage of 10 V and a gate voltage of 20 V , thereby demonstrating a big advantage of the multi-gate device design to reduce the leakage current. The results have shown that the optimised 1 µm gate length SJ-MGFET device oﬀers a speciﬁc on-resistance of 0.21 mΩ.cm2 and a breakdown voltage of 65 V with a trench-gate depth of 2.7 µm, a pillar height of 3.6 µm and a drift region length of 3.5 µm. In addition, it achieves 68%, 52% and 15% reduction in the speciﬁc on-resistance compared to the reported fabricated SJ-LDMOSFET, fabricated SJ-FinFET and simulated SJ-FinFET at the same BV rating, thereby capable of oﬀering a better performance in terms of a high drive current, a maximum breakdown voltage, a minimum speciﬁc on-resistance, and excellent FoM for sub - 100 V rating applications.Furthermore, the potentiality of scaling the device architecture of the optimised SJ-MGFET is examined from the 1 µm gate length to 0.5 µm, and 0.25 µm, respectively. Diﬀerent scaling approaches is carefully explored in all dimensions of the 3-D device structure in the simulations. The scaling down of the 1.0 µm gate length SJ-MGFET structure laterally (along the y-axis) by scaling the channel length, the gate length, the gate oxide thickness, and the SJ drift unit length by a factor S to shrink the gate length of 1.0 µm to 0.5 µm and 0.25 µm is examined in the simulations in this thesis. In order to prevent a weak electrostatic integrity in the scaled 0.5 µm and 0.25 µm gate lengths (Lgate) SJ-MGFETs, the doping proﬁle is optimised aiming at achieving a maximum drive current, a minimum leakage current, a high switching capability, a low speciﬁc on-resistance, and an improve avalanche capabilities of the devices. The scaled and optimised SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm achieve 30% and 63% increase in the drive current in comparison with the 1.0 µm gate length SJ-MGFET at a drain voltage of 0.1 V and a gate voltage of 15 V . Additionally, the scaled SJ-MGFETs oﬀer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V with a gate length of 0.5 µm and 0.25 µm, respectively. The SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm having a pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low speciﬁc on-resistance (Ron,sp) of 7.68 mΩ.mm2 and 2.24 mΩ.mm2 (VGS = 10 V ) and breakdown voltage (BV ) of 48 V and 26 V , respectively.Finally, the lateral scaling and optimisation of the 1 µm gate length SJ-MGFET to gate lengths of 0.5 µm and 0.25 µm using Silvaco Technology Computer Aided Design (TCAD) simulations has shown that the FoM of the non-planar transistor can be greatly improved in terms of switching speed, drive current, breakdown voltage, speciﬁc on-resistance, and physical density for a higher integration in a CMOS architecture. E-Thesis 31 12 2019 2019-12-31 10.23889/Suthesis.50915 COLLEGE NANME COLLEGE CODE Swansea University Doctoral Ph.D 2019-06-25T11:15:52.0114859 2019-06-24T16:55:41.4899757 Faculty of Science and Engineering School of Engineering and Applied Sciences - Uncategorised Olujide A. Adenekan 1 0050915-25062019110536.pdf Adenekan_Olujide_A_PhD_Thesis_Final.pdf 2019-06-25T11:05:36.6870000 Output 6268875 application/pdf E-Thesis – open access true 2019-06-24T00:00:00.0000000 true
title	Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations
spellingShingle	Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations ,
title_short	Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations
title_full	Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations
title_fullStr	Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations
title_full_unstemmed	Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations
title_sort	Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations
author	,
author2	Olujide A. Adenekan
format	E-Thesis
publishDate	2019
institution	Swansea University
doi_str_mv	10.23889/Suthesis.50915
college_str	Faculty of Science and Engineering
hierarchytype
hierarchy_top_id	facultyofscienceandengineering
hierarchy_top_title	Faculty of Science and Engineering
hierarchy_parent_id	facultyofscienceandengineering
hierarchy_parent_title	Faculty of Science and Engineering
department_str	School of Engineering and Applied Sciences - Uncategorised{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Engineering and Applied Sciences - Uncategorised
document_store_str	1
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description	A design, optimisation, and scaling of a complementary metal-oxide-semiconductor CMOS-compatible lateral super-junction (SJ) multi-gate (MG) MOSFET(SJ-MGFET) based on silicon-on-insulator (SOI) technology is examined as a pre-ferred solution in mitigating the predominance of channel resistance during operation at a low voltage. In order to overcome the preponderance of the channel resistance, the SJ-MGFET uses a non-planar 3-D embedded trench gate and a folded alternat-ing U-shaped n/p– SJ drift region pillar. The trench gate will redistribute electron current crowding near the top surface of the n− pillar reducing the channel resis-tance. The folded U-shaped n/p– pillar uniformly distributes the electric ﬁeld in the SJ drift region.The variations in the device architecture of a 1 µm gate length lateral super-junction (SJ) multi-gate MOSFET (SJ-MGFET) are explored using the physically based commercial 3-D TCAD device simulations by Silvaco. Investigation and analysis of diﬀerent carrier transport models are carried out with diﬀerent doping proﬁles by calibrating the drift-diﬀusion simulations to experimental I-V characteristics and breakdown voltage of the SJ-MGFET. The study, then aimed to improve drive current, breakdown voltage (BV ), and speciﬁc on-resistance (Ron,sp). The eﬀect of charge imbalance in the SJ pillar unit on the device breakdown voltage is studied with variations in the drift region length. It is observed that the charge imbalance in the SJ unit barely changes due to the ﬁxed ratio between the pillar width and the pillar height.It has been reported that the simulated and optimised SJ-MGFET device achieves 41% increase in the drive current with an on-oﬀ ratio of 5×106 at a drain voltage of 10 V and a gate voltage of 20 V , thereby demonstrating a big advantage of the multi-gate device design to reduce the leakage current. The results have shown that the optimised 1 µm gate length SJ-MGFET device oﬀers a speciﬁc on-resistance of 0.21 mΩ.cm2 and a breakdown voltage of 65 V with a trench-gate depth of 2.7 µm, a pillar height of 3.6 µm and a drift region length of 3.5 µm. In addition, it achieves 68%, 52% and 15% reduction in the speciﬁc on-resistance compared to the reported fabricated SJ-LDMOSFET, fabricated SJ-FinFET and simulated SJ-FinFET at the same BV rating, thereby capable of oﬀering a better performance in terms of a high drive current, a maximum breakdown voltage, a minimum speciﬁc on-resistance, and excellent FoM for sub - 100 V rating applications.Furthermore, the potentiality of scaling the device architecture of the optimised SJ-MGFET is examined from the 1 µm gate length to 0.5 µm, and 0.25 µm, respectively. Diﬀerent scaling approaches is carefully explored in all dimensions of the 3-D device structure in the simulations. The scaling down of the 1.0 µm gate length SJ-MGFET structure laterally (along the y-axis) by scaling the channel length, the gate length, the gate oxide thickness, and the SJ drift unit length by a factor S to shrink the gate length of 1.0 µm to 0.5 µm and 0.25 µm is examined in the simulations in this thesis. In order to prevent a weak electrostatic integrity in the scaled 0.5 µm and 0.25 µm gate lengths (Lgate) SJ-MGFETs, the doping proﬁle is optimised aiming at achieving a maximum drive current, a minimum leakage current, a high switching capability, a low speciﬁc on-resistance, and an improve avalanche capabilities of the devices. The scaled and optimised SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm achieve 30% and 63% increase in the drive current in comparison with the 1.0 µm gate length SJ-MGFET at a drain voltage of 0.1 V and a gate voltage of 15 V . Additionally, the scaled SJ-MGFETs oﬀer a transconductance (gm) of 20 mS/mm and 56 mS/mm at a drain voltage of 0.1 V with a gate length of 0.5 µm and 0.25 µm, respectively. The SJ-MGFETs with a gate length of 0.5 µm and 0.25 µm having a pillar of a width of 0.3 µm and a trench depth of 2.7 µm, achieve a low speciﬁc on-resistance (Ron,sp) of 7.68 mΩ.mm2 and 2.24 mΩ.mm2 (VGS = 10 V ) and breakdown voltage (BV ) of 48 V and 26 V , respectively.Finally, the lateral scaling and optimisation of the 1 µm gate length SJ-MGFET to gate lengths of 0.5 µm and 0.25 µm using Silvaco Technology Computer Aided Design (TCAD) simulations has shown that the FoM of the non-planar transistor can be greatly improved in terms of switching speed, drive current, breakdown voltage, speciﬁc on-resistance, and physical density for a higher integration in a CMOS architecture.
published_date	2019-12-31T19:55:38Z
_version_	1821436635574697984
score	11.047609

Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations / Olujide A. Adenekan

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