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Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

Olujide Adenekan, Paul Holland, Karol Kalna Orcid Logo

Microelectronics Journal, Volume: 81, Pages: 94 - 100

Swansea University Authors: Paul Holland, Karol Kalna Orcid Logo

Abstract

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental char...

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Published in: Microelectronics Journal
ISSN: 0026-2692
Published: 2018
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URI: https://cronfa.swan.ac.uk/Record/cronfa44949
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first_indexed 2018-10-18T13:20:32Z
last_indexed 2018-11-26T14:20:46Z
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2018-11-26T12:46:53.0590923</datestamp><bib-version>v2</bib-version><id>44949</id><entry>2018-10-18</entry><title>Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100&#x202F;V applications</title><swanseaauthors><author><sid>9c7eea4ea9d615fcbf2801a672dd2e7f</sid><firstname>Paul</firstname><surname>Holland</surname><name>Paul Holland</name><active>true</active><ethesisStudent>false</ethesisStudent></author><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2018-10-18</date><deptcode>EEEG</deptcode><abstract>The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100&#x202F;V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p&#x2013; SJ drift region pillar width of 0.3&#x202F;&#x3BC;m with a trench depth of 2.7&#x202F;&#x3BC;m achieves specific on-resistance (Ron,sp) of 0.21&#x202F;m&#x3A9;.cm2 at a BV of 65&#x202F;V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5&#x202F;V and a gate voltage of 10&#x202F;V.</abstract><type>Journal Article</type><journal>Microelectronics Journal</journal><volume>81</volume><paginationStart>94</paginationStart><paginationEnd>100</paginationEnd><publisher/><issnPrint>0026-2692</issnPrint><keywords>Super-junction (SJ), Multi-gate (MG), Power MOSFETs, Silicon-on-insulator (SOI), Breakdown voltage (BV), Specific on-resistance</keywords><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2018</publishedYear><publishedDate>2018-12-31</publishedDate><doi>10.1016/j.mejo.2018.09.007</doi><url/><notes/><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2018-11-26T12:46:53.0590923</lastEdited><Created>2018-10-18T10:13:20.0144613</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Olujide</firstname><surname>Adenekan</surname><order>1</order></author><author><firstname>Paul</firstname><surname>Holland</surname><order>2</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>3</order></author></authors><documents><document><filename>0044949-19102018083129.pdf</filename><originalFilename>adenekan2018v2.pdf</originalFilename><uploaded>2018-10-19T08:31:29.6030000</uploaded><type>Output</type><contentLength>1620853</contentLength><contentType>application/pdf</contentType><version>Accepted Manuscript</version><cronfaStatus>true</cronfaStatus><embargoDate>2019-09-28T00:00:00.0000000</embargoDate><copyrightCorrect>true</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807>
spelling 2018-11-26T12:46:53.0590923 v2 44949 2018-10-18 Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications 9c7eea4ea9d615fcbf2801a672dd2e7f Paul Holland Paul Holland true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2018-10-18 EEEG The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V. Journal Article Microelectronics Journal 81 94 100 0026-2692 Super-junction (SJ), Multi-gate (MG), Power MOSFETs, Silicon-on-insulator (SOI), Breakdown voltage (BV), Specific on-resistance 31 12 2018 2018-12-31 10.1016/j.mejo.2018.09.007 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2018-11-26T12:46:53.0590923 2018-10-18T10:13:20.0144613 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Olujide Adenekan 1 Paul Holland 2 Karol Kalna 0000-0002-6333-9189 3 0044949-19102018083129.pdf adenekan2018v2.pdf 2018-10-19T08:31:29.6030000 Output 1620853 application/pdf Accepted Manuscript true 2019-09-28T00:00:00.0000000 true eng
title Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
spellingShingle Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
Paul Holland
Karol Kalna
title_short Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_full Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_fullStr Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_full_unstemmed Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
title_sort Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications
author_id_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f
1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f_***_Paul Holland
1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Paul Holland
Karol Kalna
author2 Olujide Adenekan
Paul Holland
Karol Kalna
format Journal article
container_title Microelectronics Journal
container_volume 81
container_start_page 94
publishDate 2018
institution Swansea University
issn 0026-2692
doi_str_mv 10.1016/j.mejo.2018.09.007
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V.
published_date 2018-12-31T03:56:27Z
_version_ 1763752843758534656
score 10.99342