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FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Daniel Nagy, Guillermo Indalecio, Antonio J. Garcia-Loureiro, Muhammad A. Elmessary, Karol Kalna Orcid Logo, Natalia Seoane

IEEE Journal of the Electron Devices Society, Volume: 6, Pages: 332 - 340

Swansea University Authors: Daniel Nagy, Karol Kalna Orcid Logo

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DOI (Published version): 10.1109/JEDS.2018.2804383

Abstract

Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm...

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Published in: IEEE Journal of the Electron Devices Society
ISSN: 2168-6734 2168-6734
Published: 2018
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URI: https://cronfa.swan.ac.uk/Record/cronfa38852
first_indexed 2018-02-22T19:51:39Z
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2020-12-17T10:47:42.7658873</datestamp><bib-version>v2</bib-version><id>38852</id><entry>2018-02-22</entry><title>FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability</title><swanseaauthors><author><sid>f6efefac27b3523cc876c78741c44643</sid><firstname>Daniel</firstname><surname>Nagy</surname><name>Daniel Nagy</name><active>true</active><ethesisStudent>false</ethesisStudent></author><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2018-02-22</date><abstract>Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures.</abstract><type>Journal Article</type><journal>IEEE Journal of the Electron Devices Society</journal><volume>6</volume><journalNumber/><paginationStart>332</paginationStart><paginationEnd>340</paginationEnd><publisher/><placeOfPublication/><isbnPrint/><isbnElectronic/><issnPrint>2168-6734</issnPrint><issnElectronic>2168-6734</issnElectronic><keywords>Logic gates, FinFETs, Gallium arsenide, Silicon, Nanoscale devices ,Metals, Semiconductor process modeling</keywords><publishedDay>2</publishedDay><publishedMonth>3</publishedMonth><publishedYear>2018</publishedYear><publishedDate>2018-03-02</publishedDate><doi>10.1109/JEDS.2018.2804383</doi><url/><notes/><college>COLLEGE NANME</college><CollegeCode>COLLEGE CODE</CollegeCode><institution>Swansea University</institution><apcterm/><lastEdited>2020-12-17T10:47:42.7658873</lastEdited><Created>2018-02-22T15:58:17.4791539</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Daniel</firstname><surname>Nagy</surname><order>1</order></author><author><firstname>Guillermo</firstname><surname>Indalecio</surname><order>2</order></author><author><firstname>Antonio J.</firstname><surname>Garcia-Loureiro</surname><order>3</order></author><author><firstname>Muhammad A.</firstname><surname>Elmessary</surname><order>4</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>5</order></author><author><firstname>Natalia</firstname><surname>Seoane</surname><order>6</order></author></authors><documents><document><filename>38852__8075__c91c27fb21c449d2bcc293cbfa8ad9c9.pdf</filename><originalFilename>nagy2018.pdf</originalFilename><uploaded>2018-02-22T16:01:38.1930000</uploaded><type>Output</type><contentLength>5548783</contentLength><contentType>application/pdf</contentType><version>Proof</version><cronfaStatus>true</cronfaStatus><embargoDate>2018-02-22T00:00:00.0000000</embargoDate><documentNotes>&#xA9; 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission</documentNotes><copyrightCorrect>true</copyrightCorrect><language>eng</language></document><document><filename>0038852-23042018151500.pdf</filename><originalFilename>NagyFinFet2018.pdf</originalFilename><uploaded>2018-04-23T15:15:00.5530000</uploaded><type>Output</type><contentLength>1877199</contentLength><contentType>application/pdf</contentType><version>Version of Record</version><cronfaStatus>true</cronfaStatus><documentNotes>&#xA9; 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission</documentNotes><copyrightCorrect>true</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807>
spelling 2020-12-17T10:47:42.7658873 v2 38852 2018-02-22 FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability f6efefac27b3523cc876c78741c44643 Daniel Nagy Daniel Nagy true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2018-02-22 Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures. Journal Article IEEE Journal of the Electron Devices Society 6 332 340 2168-6734 2168-6734 Logic gates, FinFETs, Gallium arsenide, Silicon, Nanoscale devices ,Metals, Semiconductor process modeling 2 3 2018 2018-03-02 10.1109/JEDS.2018.2804383 COLLEGE NANME COLLEGE CODE Swansea University 2020-12-17T10:47:42.7658873 2018-02-22T15:58:17.4791539 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Daniel Nagy 1 Guillermo Indalecio 2 Antonio J. Garcia-Loureiro 3 Muhammad A. Elmessary 4 Karol Kalna 0000-0002-6333-9189 5 Natalia Seoane 6 38852__8075__c91c27fb21c449d2bcc293cbfa8ad9c9.pdf nagy2018.pdf 2018-02-22T16:01:38.1930000 Output 5548783 application/pdf Proof true 2018-02-22T00:00:00.0000000 © 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission true eng 0038852-23042018151500.pdf NagyFinFet2018.pdf 2018-04-23T15:15:00.5530000 Output 1877199 application/pdf Version of Record true © 2018 IEEE. Translations and content mining are permitted for academic research only. Personal use is also permitted, but republication/redistribution requires IEEE permission true eng
title FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
spellingShingle FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
Daniel Nagy
Karol Kalna
title_short FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
title_full FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
title_fullStr FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
title_full_unstemmed FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
title_sort FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
author_id_str_mv f6efefac27b3523cc876c78741c44643
1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv f6efefac27b3523cc876c78741c44643_***_Daniel Nagy
1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Daniel Nagy
Karol Kalna
author2 Daniel Nagy
Guillermo Indalecio
Antonio J. Garcia-Loureiro
Muhammad A. Elmessary
Karol Kalna
Natalia Seoane
format Journal article
container_title IEEE Journal of the Electron Devices Society
container_volume 6
container_start_page 332
publishDate 2018
institution Swansea University
issn 2168-6734
2168-6734
doi_str_mv 10.1109/JEDS.2018.2804383
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description Performance, scalability and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3D simulation tools. Two experimentally based devices, a 25 nm gate length FinFET and a 22 nm GAA NW are modelled and then scaled down to 10.7 and 10 nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7 nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10 nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the sub-threshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7 nm FinFET than that for the 10 nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6 nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 110 channel orientation is more resilient to the MGG and LER variability in both architectures.
published_date 2018-03-02T07:23:37Z
_version_ 1821389322642784256
score 11.047501

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