No Cover Image

Journal article 1116 views 206 downloads

Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes

N Seoane, M Aldegunde, D Nagy, M A Elmessary, G Indalecio, A J García-Loureiro, K Kalna, Karol Kalna Orcid Logo

Semiconductor Science and Technology, Volume: 31, Issue: 7, Start page: 075005

Swansea University Author: Karol Kalna Orcid Logo

DOI (Published version): 10.1088/0268-1242/31/7/075005

Abstract

We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFET...

Full description

Published in: Semiconductor Science and Technology
Published: 2016
URI: https://cronfa.swan.ac.uk/Record/cronfa29411
Tags: Add Tag
No Tags, Be the first to tag this record!
first_indexed 2016-08-02T19:01:23Z
last_indexed 2018-02-09T05:14:26Z
id cronfa29411
recordtype SURis
fullrecord <?xml version="1.0"?><rfc1807><datestamp>2016-10-03T16:44:55.7629420</datestamp><bib-version>v2</bib-version><id>29411</id><entry>2016-08-02</entry><title>Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes</title><swanseaauthors><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2016-08-02</date><deptcode>EEEG</deptcode><abstract>We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 &#xD7; 104 when L G = 12.8 nm and 5.7 &#xD7; 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts.</abstract><type>Journal Article</type><journal>Semiconductor Science and Technology</journal><volume>31</volume><journalNumber>7</journalNumber><paginationStart>075005</paginationStart><publisher/><keywords/><publishedDay>9</publishedDay><publishedMonth>6</publishedMonth><publishedYear>2016</publishedYear><publishedDate>2016-06-09</publishedDate><doi>10.1088/0268-1242/31/7/075005</doi><url/><notes/><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2016-10-03T16:44:55.7629420</lastEdited><Created>2016-08-02T15:32:07.7934815</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>N</firstname><surname>Seoane</surname><order>1</order></author><author><firstname>M</firstname><surname>Aldegunde</surname><order>2</order></author><author><firstname>D</firstname><surname>Nagy</surname><order>3</order></author><author><firstname>M A</firstname><surname>Elmessary</surname><order>4</order></author><author><firstname>G</firstname><surname>Indalecio</surname><order>5</order></author><author><firstname>A J</firstname><surname>Garc&#xED;a-Loureiro</surname><order>6</order></author><author><firstname>K</firstname><surname>Kalna</surname><order>7</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>8</order></author></authors><documents><document><filename>0029411-982016110641AM.pdf</filename><originalFilename>Seoane2016(2).pdf</originalFilename><uploaded>2016-09-08T11:06:41.9130000</uploaded><type>Output</type><contentLength>2208403</contentLength><contentType>application/pdf</contentType><version>Accepted Manuscript</version><cronfaStatus>true</cronfaStatus><embargoDate>2017-06-09T00:00:00.0000000</embargoDate><copyrightCorrect>true</copyrightCorrect></document></documents><OutputDurs/></rfc1807>
spelling 2016-10-03T16:44:55.7629420 v2 29411 2016-08-02 Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2016-08-02 EEEG We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 × 104 when L G = 12.8 nm and 5.7 × 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts. Journal Article Semiconductor Science and Technology 31 7 075005 9 6 2016 2016-06-09 10.1088/0268-1242/31/7/075005 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2016-10-03T16:44:55.7629420 2016-08-02T15:32:07.7934815 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering N Seoane 1 M Aldegunde 2 D Nagy 3 M A Elmessary 4 G Indalecio 5 A J García-Loureiro 6 K Kalna 7 Karol Kalna 0000-0002-6333-9189 8 0029411-982016110641AM.pdf Seoane2016(2).pdf 2016-09-08T11:06:41.9130000 Output 2208403 application/pdf Accepted Manuscript true 2017-06-09T00:00:00.0000000 true
title Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
spellingShingle Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
Karol Kalna
title_short Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
title_full Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
title_fullStr Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
title_full_unstemmed Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
title_sort Simulation study of scaled In0.53Ga0.47As and Si FinFETs for sub-16 nm technology nodes
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Karol Kalna
author2 N Seoane
M Aldegunde
D Nagy
M A Elmessary
G Indalecio
A J García-Loureiro
K Kalna
Karol Kalna
format Journal article
container_title Semiconductor Science and Technology
container_volume 31
container_issue 7
container_start_page 075005
publishDate 2016
institution Swansea University
doi_str_mv 10.1088/0268-1242/31/7/075005
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description We investigate the performance and scalability of III-V-OI In0.53Ga0.47As and SOI Si FinFETs using state-of-the-art in-house-built 3D simulation tools. Three different technology nodes specified in the ITRS have been analysed with gate lengths (L G) of 14.0 nm, 12.8 and 10.4 nm for the InGaAs FinFETs and 12.8 nm, 10.7 and 8.1 nm for the Si devices. At a high drain bias, the 12.8 and 10.4 nm InGaAs FinFETs deliver 15% and 13% larger on-currents but 14% larger off-currents than the equivalent 12.8 and 10.7 nm Si FinFETs, respectively. For equivalent gate lengths, both the InGaAs and the Si FinFETs have the same I ON/I OFF ratio (5.9 × 104 when L G = 12.8 nm and 5.7 × 104 when L G = 10.4(10.7) nm). A more pronounced S/D tunnelling affecting the InGaAs FinFETs leads to a larger deterioration in their SS (less than 10%) and DIBL (around 20%) compared to the Si counterparts.
published_date 2016-06-09T03:35:46Z
_version_ 1763751541909487616
score 11.013619

Similar Items