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The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study

Murad Alabdullah, N. Seoane Orcid Logo, A. J. Garcia-Loureiro Orcid Logo, Karol Kalna Orcid Logo

IEEE Journal of the Electron Devices Society, Volume: 14, Pages: 324 - 334

Swansea University Authors: Murad Alabdullah, Karol Kalna Orcid Logo

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DOI (Published version): 10.1109/jeds.2026.3694652

Abstract

The gate scaling to an ultimate length of 8 nm in Si nanosheet (NS) and nanowire (NW) field-effect transistors (FETs) results in a notable reduction in the drain drive current ( IDD ), despite conventional scaling theory predicting an increase. Using advanced 3D finite element ensemble Monte Carlo (...

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Published in: IEEE Journal of the Electron Devices Society
ISSN: 2168-6734
Published: Institute of Electrical and Electronics Engineers (IEEE) 2026
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URI: https://cronfa.swan.ac.uk/Record/cronfa72178
first_indexed 2026-06-26T14:51:41Z
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spelling 2026-06-26T15:52:40.3679609 v2 72178 2026-06-26 The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study d6f2e878d2e82c7f12a1e314a4ea07e5 Murad Alabdullah Murad Alabdullah true false 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2026-06-26 The gate scaling to an ultimate length of 8 nm in Si nanosheet (NS) and nanowire (NW) field-effect transistors (FETs) results in a notable reduction in the drain drive current ( IDD ), despite conventional scaling theory predicting an increase. Using advanced 3D finite element ensemble Monte Carlo (MC) simulations with Schrödinger equation quantum corrections, we investigate the impact of gate scaling from 22 nm to 8 nm in gate-all-around (GAA) NS and NW FETs. Our results indicate that while IDD initially increases for a gate length scaled from 22 nm to 16 nm as expected, further scaling to sub-16 nm lengths leads to a decline of up to 18% in NS FETs and 20% in NW FETs at 8 nm. This IDD reduction is mainly due to enhanced long-range Coulomb interactions between the source and the drain, inducing fringing electric fields at the source gate-edge in addition to already present fringing electric fields at the drain gate-edge, leading to increased channel back-scattering. Journal Article IEEE Journal of the Electron Devices Society 14 324 334 Institute of Electrical and Electronics Engineers (IEEE) 2168-6734 Nanosheet FET, nanowire FET, quantum confinement, fringing electric fields, backscattering effects 31 12 2026 2026-12-31 10.1109/jeds.2026.3694652 COLLEGE NANME COLLEGE CODE Swansea University Other 2026-06-26T15:52:40.3679609 2026-06-26T15:34:10.0282351 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Murad Alabdullah 1 N. Seoane 0000-0003-0973-461X 2 A. J. Garcia-Loureiro 0000-0003-0574-1513 3 Karol Kalna 0000-0002-6333-9189 4 72178__37064__37e6f9d592bb4358b251e876c5b19756.pdf 72178.VOR.pdf 2026-06-26T15:50:49.1835974 Output 1425023 application/pdf Version of Record true 2026 The Authors. This work is licensed under a Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License. true eng https://creativecommons.org/licenses/by-nc-nd/4.0/
title The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study
spellingShingle The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study
Murad Alabdullah
Karol Kalna
title_short The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study
title_full The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study
title_fullStr The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study
title_full_unstemmed The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study
title_sort The Effect of Gate Scaling on Drain Current in Ultra-Scaled Nanosheet and Nanowire FETs: A 3D Monte Carlo Simulation Study
author_id_str_mv d6f2e878d2e82c7f12a1e314a4ea07e5
1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv d6f2e878d2e82c7f12a1e314a4ea07e5_***_Murad Alabdullah
1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Murad Alabdullah
Karol Kalna
author2 Murad Alabdullah
N. Seoane
A. J. Garcia-Loureiro
Karol Kalna
format Journal article
container_title IEEE Journal of the Electron Devices Society
container_volume 14
container_start_page 324
publishDate 2026
institution Swansea University
issn 2168-6734
doi_str_mv 10.1109/jeds.2026.3694652
publisher Institute of Electrical and Electronics Engineers (IEEE)
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description The gate scaling to an ultimate length of 8 nm in Si nanosheet (NS) and nanowire (NW) field-effect transistors (FETs) results in a notable reduction in the drain drive current ( IDD ), despite conventional scaling theory predicting an increase. Using advanced 3D finite element ensemble Monte Carlo (MC) simulations with Schrödinger equation quantum corrections, we investigate the impact of gate scaling from 22 nm to 8 nm in gate-all-around (GAA) NS and NW FETs. Our results indicate that while IDD initially increases for a gate length scaled from 22 nm to 16 nm as expected, further scaling to sub-16 nm lengths leads to a decline of up to 18% in NS FETs and 20% in NW FETs at 8 nm. This IDD reduction is mainly due to enhanced long-range Coulomb interactions between the source and the drain, inducing fringing electric fields at the source gate-edge in addition to already present fringing electric fields at the drain gate-edge, leading to increased channel back-scattering.
published_date 2026-12-31T06:26:31Z
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score 11.110583

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