On short channel effects in high voltage JFETs: A theoretical analysis

Monaghan, Finn; Muniz, Antonio Martinez; Evans, J.; Fisher, C.; Jennings, M.

doi:10.1016/j.pedc.2024.100057

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On short channel effects in high voltage JFETs: A theoretical analysis

Finn Monaghan, Antonio Martinez Muniz

, J. Evans, C. Fisher, M. Jennings

Power Electronic Devices and Components, Volume: 7, Start page: 100057

Swansea University Authors: Finn Monaghan, Antonio Martinez Muniz

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DOI (Published version): 10.1016/j.pedc.2024.100057

Abstract

In this work, the impact of Short Channel Effects (SCEs), particularly Drain Induced Barrier Lowering (DIBL) on the performance of a high voltage Silicon Carbide (SiC) JFET has been thoroughly investigated. Drift-Diffusion simulations of on-state current-voltage characteristics and breakdown perform...

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Published in:	Power Electronic Devices and Components
ISSN:	2772-3704
Published:	Elsevier BV 2024
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spelling	v2 66247 2024-05-02 On short channel effects in high voltage JFETs: A theoretical analysis 5a628866e0e707d66c657b84e4ca8c9a Finn Monaghan Finn Monaghan true false cd433784251add853672979313f838ec 0000-0001-8131-7242 Antonio Martinez Muniz Antonio Martinez Muniz true false 2024-05-02 In this work, the impact of Short Channel Effects (SCEs), particularly Drain Induced Barrier Lowering (DIBL) on the performance of a high voltage Silicon Carbide (SiC) JFET has been thoroughly investigated. Drift-Diffusion simulations of on-state current-voltage characteristics and breakdown performance have been completed for different gate junction depths (xj) and mesa widths (MW). Due to the short channel length, realistic implant doping profiles extracted from experimentally calibrated Monte-Carlo based SRIM simulations have been used. Two suitable designs to eliminate premature DIBL-induced failure have been found: xj = 0.7 µm for MW=1.75 µm, and xj = 1 µm for MW=2 µm. We found that a 0.3 µm junction depth has a breakdown voltage of only 50 V due to collapse of the source-drain barrier at a relatively low drain bias. Threshold voltage (Vth) decreases with increasing junction depth, approaching 0 V. This is due to a combination of greater lateral straggling of implanted ions and improved electrostatic control of the channel. Our calculations demonstrate that the most robust option to mitigate DIBL and consequently early breakdown is to maintain xj ≥1 µm. At this depth, the threshold voltage has a weak dependence on drain bias, indicating diminishing SCEs. Decreasing the mesa width mitigates early breakdown but requires a mesa width of less than 1.75 µm, which poses fabrication challenges.Keywords: Silicon carbide; JFET; Drain induced barrier lowering; Short channel effects; Breakdown voltage; Model Journal Article Power Electronic Devices and Components 7 100057 Elsevier BV 2772-3704 Silicon carbide; JFET; Drain induced barrier lowering; Short channel effects; Breakdown voltage; Model 1 4 2024 2024-04-01 10.1016/j.pedc.2024.100057 COLLEGE NANME COLLEGE CODE Swansea University Not Required The authors would like to acknowledge the COATED M2A funding from the European Social Fund via the Welsh Government (c80816), the Engineering and Physical Sciences Research Council (Grant Ref: EP/ S02252X/1). 2024-06-19T12:39:29.7076403 2024-05-02T16:14:58.5652034 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Finn Monaghan 1 Antonio Martinez Muniz 0000-0001-8131-7242 2 J. Evans 3 C. Fisher 4 M. Jennings 5 66247__30677__2505acd9107b401e93d491e7941f374a.pdf 66247.VoR.pdf 2024-06-19T12:34:38.1888200 Output 4130576 application/pdf Version of Record true ©2024TheAuthor(s). This is an open access article under the CC BY-NC-ND license. true eng http://creativecommons.org/licenses/bync-nd/4.0/
title	On short channel effects in high voltage JFETs: A theoretical analysis
spellingShingle	On short channel effects in high voltage JFETs: A theoretical analysis Finn Monaghan Antonio Martinez Muniz
title_short	On short channel effects in high voltage JFETs: A theoretical analysis
title_full	On short channel effects in high voltage JFETs: A theoretical analysis
title_fullStr	On short channel effects in high voltage JFETs: A theoretical analysis
title_full_unstemmed	On short channel effects in high voltage JFETs: A theoretical analysis
title_sort	On short channel effects in high voltage JFETs: A theoretical analysis
author_id_str_mv	5a628866e0e707d66c657b84e4ca8c9a cd433784251add853672979313f838ec
author_id_fullname_str_mv	5a628866e0e707d66c657b84e4ca8c9a_*_Finn Monaghan cd433784251add853672979313f838ec_*_Antonio Martinez Muniz
author	Finn Monaghan Antonio Martinez Muniz
author2	Finn Monaghan Antonio Martinez Muniz J. Evans C. Fisher M. Jennings
format	Journal article
container_title	Power Electronic Devices and Components
container_volume	7
container_start_page	100057
publishDate	2024
institution	Swansea University
issn	2772-3704
doi_str_mv	10.1016/j.pedc.2024.100057
publisher	Elsevier BV
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department_str	School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
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description	In this work, the impact of Short Channel Effects (SCEs), particularly Drain Induced Barrier Lowering (DIBL) on the performance of a high voltage Silicon Carbide (SiC) JFET has been thoroughly investigated. Drift-Diffusion simulations of on-state current-voltage characteristics and breakdown performance have been completed for different gate junction depths (xj) and mesa widths (MW). Due to the short channel length, realistic implant doping profiles extracted from experimentally calibrated Monte-Carlo based SRIM simulations have been used. Two suitable designs to eliminate premature DIBL-induced failure have been found: xj = 0.7 µm for MW=1.75 µm, and xj = 1 µm for MW=2 µm. We found that a 0.3 µm junction depth has a breakdown voltage of only 50 V due to collapse of the source-drain barrier at a relatively low drain bias. Threshold voltage (Vth) decreases with increasing junction depth, approaching 0 V. This is due to a combination of greater lateral straggling of implanted ions and improved electrostatic control of the channel. Our calculations demonstrate that the most robust option to mitigate DIBL and consequently early breakdown is to maintain xj ≥1 µm. At this depth, the threshold voltage has a weak dependence on drain bias, indicating diminishing SCEs. Decreasing the mesa width mitigates early breakdown but requires a mesa width of less than 1.75 µm, which poses fabrication challenges.Keywords: Silicon carbide; JFET; Drain induced barrier lowering; Short channel effects; Breakdown voltage; Model
published_date	2024-04-01T12:39:28Z
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score	11.037275

On short channel effects in high voltage JFETs: A theoretical analysis

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