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Conference Paper/Proceeding/Abstract 972 views 297 downloads

Injecting FPGA Configuration Faults in Parallel

Shane Fleming, David Thomas

2018 International Conference on Field-Programmable Technology (FPT)

Swansea University Author: Shane Fleming

DOI (Published version): 10.1109/fpt.2018.00037

Abstract

When using SRAM-based FPGA devices in safety critical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challeng...

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Published in: 2018 International Conference on Field-Programmable Technology (FPT)
ISBN: 978-1-7281-0215-3 978-1-7281-0214-6
Published: IEEE 2019
URI: https://cronfa.swan.ac.uk/Record/cronfa57991
first_indexed 2021-09-20T19:53:44Z
last_indexed 2021-11-25T04:16:49Z
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spelling 2021-11-24T16:37:34.5341917 v2 57991 2021-09-20 Injecting FPGA Configuration Faults in Parallel fe23ad3ebacc194b4f4c480fdde55b95 Shane Fleming Shane Fleming true false 2021-09-20 MACS When using SRAM-based FPGA devices in safety critical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challenges. In this paper, we present a framework and a concrete implementation of a parallel fault injection cluster that addresses these challenges. Scalability is addressed by using multiple identical FPGA devices, each testing a different region in parallel. Reliability is addressed by using reconfigurable system-on-chip devices, that are isolated from each other. Flexibility is addressed by using a pending commit structure, that continually checkpoints the overall experiment and allows elastic scaling. We test and showcase our approach by exhaustively flipping every bit in the configuration memory of the CHStone benchmark suite and a VivadoHLS generated k-means clustering image processing application. Our results show that: linear scaling is possible as the number of devices increases; the majority of error inducing bitflips in the k-means application do not significantly impact the output; and that the Xilinx Essential bits tool may miss some bits that can induce errors. Conference Paper/Proceeding/Abstract 2018 International Conference on Field-Programmable Technology (FPT) IEEE 978-1-7281-0215-3 978-1-7281-0214-6 20 6 2019 2019-06-20 10.1109/fpt.2018.00037 COLLEGE NANME Mathematics and Computer Science School COLLEGE CODE MACS Swansea University Another institution paid the OA fee EPSRC Doctoral Training Centre 2021-11-24T16:37:34.5341917 2021-09-20T20:38:31.8063823 College of Science College of Science Shane Fleming 1 David Thomas 2 57991__20948__f9772517b7034ae492e4608187454308.pdf fpt_2018_parallel_fault_injection.pdf 2021-09-20T20:52:03.0276058 Output 1357387 application/pdf Accepted Manuscript true true eng
title Injecting FPGA Configuration Faults in Parallel
spellingShingle Injecting FPGA Configuration Faults in Parallel
Shane Fleming
title_short Injecting FPGA Configuration Faults in Parallel
title_full Injecting FPGA Configuration Faults in Parallel
title_fullStr Injecting FPGA Configuration Faults in Parallel
title_full_unstemmed Injecting FPGA Configuration Faults in Parallel
title_sort Injecting FPGA Configuration Faults in Parallel
author_id_str_mv fe23ad3ebacc194b4f4c480fdde55b95
author_id_fullname_str_mv fe23ad3ebacc194b4f4c480fdde55b95_***_Shane Fleming
author Shane Fleming
author2 Shane Fleming
David Thomas
format Conference Paper/Proceeding/Abstract
container_title 2018 International Conference on Field-Programmable Technology (FPT)
publishDate 2019
institution Swansea University
isbn 978-1-7281-0215-3
978-1-7281-0214-6
doi_str_mv 10.1109/fpt.2018.00037
publisher IEEE
college_str College of Science
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hierarchy_top_title College of Science
hierarchy_parent_id collegeofscience
hierarchy_parent_title College of Science
department_str College of Science{{{_:::_}}}College of Science{{{_:::_}}}College of Science
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description When using SRAM-based FPGA devices in safety critical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challenges. In this paper, we present a framework and a concrete implementation of a parallel fault injection cluster that addresses these challenges. Scalability is addressed by using multiple identical FPGA devices, each testing a different region in parallel. Reliability is addressed by using reconfigurable system-on-chip devices, that are isolated from each other. Flexibility is addressed by using a pending commit structure, that continually checkpoints the overall experiment and allows elastic scaling. We test and showcase our approach by exhaustively flipping every bit in the configuration memory of the CHStone benchmark suite and a VivadoHLS generated k-means clustering image processing application. Our results show that: linear scaling is possible as the number of devices increases; the majority of error inducing bitflips in the k-means application do not significantly impact the output; and that the Xilinx Essential bits tool may miss some bits that can induce errors.
published_date 2019-06-20T02:21:29Z
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score 11.04748

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