Conference Paper/Proceeding/Abstract 643 views 260 downloads
Injecting FPGA Configuration Faults in Parallel
Shane Fleming,
David Thomas
2018 International Conference on Field-Programmable Technology (FPT)
Swansea University Author: Shane Fleming
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DOI (Published version): 10.1109/fpt.2018.00037
Abstract
When using SRAM-based FPGA devices in safety critical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challeng...
| Published in: | 2018 International Conference on Field-Programmable Technology (FPT) |
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| ISBN: | 978-1-7281-0215-3 978-1-7281-0214-6 |
| Published: |
IEEE
2019
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| URI: | https://cronfa.swan.ac.uk/Record/cronfa57991 |
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| Abstract: |
When using SRAM-based FPGA devices in safety critical applications testing against bitflips in the device configuration memory is essential. Often such tests are achieved by corrupting configuration memory bits of a running device, but this has many scalability, reliability, and flexibility challenges. In this paper, we present a framework and a concrete implementation of a parallel fault injection cluster that addresses these challenges. Scalability is addressed by using multiple identical FPGA devices, each testing a different region in parallel. Reliability is addressed by using reconfigurable system-on-chip devices, that are isolated from each other. Flexibility is addressed by using a pending commit structure, that continually checkpoints the overall experiment and allows elastic scaling. We test and showcase our approach by exhaustively flipping every bit in the configuration memory of the CHStone benchmark suite and a VivadoHLS generated k-means clustering image processing application. Our results show that: linear scaling is possible as the number of devices increases; the majority of error inducing bitflips in the k-means application do not significantly impact the output; and that the Xilinx Essential bits tool may miss some bits that can induce errors. |
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| College: |
College of Science |
| Funders: |
EPSRC Doctoral Training Centre |