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Conference Paper/Proceeding/Abstract 1369 views

Optimisation of 100V high side LDMOS using multiple simulation techniques

M Elwin, P Holland, I Anteney, J Ellis, L Armstrong, G Birchby, P Igic, Paul Holland

Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on, Pages: 104 - 107

Swansea University Author: Paul Holland

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DOI (Published version): 10.1109/ISPSD.2009.5158012

Published in: Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on
ISSN: 1943-653X
Published: 2009
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa5750
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first_indexed 2013-07-23T11:53:37Z
last_indexed 2018-02-09T04:32:29Z
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spelling 2015-03-31T11:45:37.1132974 v2 5750 2013-09-03 Optimisation of 100V high side LDMOS using multiple simulation techniques 9c7eea4ea9d615fcbf2801a672dd2e7f Paul Holland Paul Holland true false 2013-09-03 EEEG Conference Paper/Proceeding/Abstract Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on 104 107 1943-653X 31 12 2009 2009-12-31 10.1109/ISPSD.2009.5158012 This paper presents state-of-the-art 2-D and 3-D finite element techniques in CMOS design to implement a now commercially available CMOS High Voltage Platform designed by Dr Holland at Swansea University in Collaboration with the largest two semiconductor companies in the UK. COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2015-03-31T11:45:37.1132974 2013-09-03T06:20:03.0000000 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering M Elwin 1 P Holland 2 I Anteney 3 J Ellis 4 L Armstrong 5 G Birchby 6 P Igic 7 Paul Holland 8
title Optimisation of 100V high side LDMOS using multiple simulation techniques
spellingShingle Optimisation of 100V high side LDMOS using multiple simulation techniques
Paul Holland
title_short Optimisation of 100V high side LDMOS using multiple simulation techniques
title_full Optimisation of 100V high side LDMOS using multiple simulation techniques
title_fullStr Optimisation of 100V high side LDMOS using multiple simulation techniques
title_full_unstemmed Optimisation of 100V high side LDMOS using multiple simulation techniques
title_sort Optimisation of 100V high side LDMOS using multiple simulation techniques
author_id_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f
author_id_fullname_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f_***_Paul Holland
author Paul Holland
author2 M Elwin
P Holland
I Anteney
J Ellis
L Armstrong
G Birchby
P Igic
Paul Holland
format Conference Paper/Proceeding/Abstract
container_title Power Semiconductor Devices & IC's, 2009. ISPSD 2009. 21st International Symposium on
container_start_page 104
publishDate 2009
institution Swansea University
issn 1943-653X
doi_str_mv 10.1109/ISPSD.2009.5158012
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 0
active_str 0
published_date 2009-12-31T03:06:57Z
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score 11.013799

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