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LDMOSFET with drain potential suppression for 100V Power IC technology

P Holland, M Elwin, I Anteney, J Ellis, L Armstrong, G Birchby, P Igic, Paul Holland

Microelectronics Reliability, Volume: 51, Issue: 3, Pages: 529 - 535

Swansea University Author: Paul Holland

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DOI (Published version): 10.1016/j.microrel.2010.09.015

Published in: Microelectronics Reliability
ISSN: 0026-2714
Published: 2011
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URI: https://cronfa.swan.ac.uk/Record/cronfa5749
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first_indexed 2013-07-23T11:53:36Z
last_indexed 2018-02-09T04:32:29Z
id cronfa5749
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2015-03-31T11:45:26.7084976</datestamp><bib-version>v2</bib-version><id>5749</id><entry>2013-09-03</entry><title>LDMOSFET with drain potential suppression for 100V Power IC technology</title><swanseaauthors><author><sid>9c7eea4ea9d615fcbf2801a672dd2e7f</sid><firstname>Paul</firstname><surname>Holland</surname><name>Paul Holland</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2013-09-03</date><deptcode>EEEG</deptcode><abstract></abstract><type>Journal Article</type><journal>Microelectronics Reliability</journal><volume>51</volume><journalNumber>3</journalNumber><paginationStart>529</paginationStart><paginationEnd>535</paginationEnd><publisher/><issnPrint>0026-2714</issnPrint><issnElectronic/><keywords/><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2011</publishedYear><publishedDate>2011-12-31</publishedDate><doi>10.1016/j.microrel.2010.09.015</doi><url/><notes>A &#xA3;1M WAG KEF grant to Swansea generated many high impact papers subitted to RAE.These activities and publications triggered world-wide interest and Diodes ZETEX, one of the world&#x2019;s largest semiconductor manufacturers and its engineers tested Swansea&#x2019;s designed silicon chips and verified the findings. The cooperation with Diodes ZETEX and X-Fab led to an &#xA3;1M Power System on Chip Development DTI grant (2006 - 2009). The industrial part of the DTI funded research was led by Prof Glenn Birchby, Chief Scientist at Diodes, and Dr Brendan Bold, Process Development Director, X-Fab Semiconductor Foundries. After the completion, the grant has been marked excellent by the TSB and achieved 95% of its targets. This paper reports on the outputs of the project. The LDMOS transistors designed by Swansea reduced the On-Resistance by more than half compared to X-Fab's previous design. They also extended the breakdwon voltage to more than 100V allowing modern LED lighting control designs to be introduced into CMOS. The papers reports how Dr Holland et al successfully transferred technology to a silicon foundry and is being used for high voltgae Power IC designs.</notes><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2015-03-31T11:45:26.7084976</lastEdited><Created>2013-09-03T06:20:05.0000000</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>P</firstname><surname>Holland</surname><order>1</order></author><author><firstname>M</firstname><surname>Elwin</surname><order>2</order></author><author><firstname>I</firstname><surname>Anteney</surname><order>3</order></author><author><firstname>J</firstname><surname>Ellis</surname><order>4</order></author><author><firstname>L</firstname><surname>Armstrong</surname><order>5</order></author><author><firstname>G</firstname><surname>Birchby</surname><order>6</order></author><author><firstname>P</firstname><surname>Igic</surname><order>7</order></author><author><firstname>Paul</firstname><surname>Holland</surname><order>8</order></author></authors><documents/><OutputDurs/></rfc1807>
spelling 2015-03-31T11:45:26.7084976 v2 5749 2013-09-03 LDMOSFET with drain potential suppression for 100V Power IC technology 9c7eea4ea9d615fcbf2801a672dd2e7f Paul Holland Paul Holland true false 2013-09-03 EEEG Journal Article Microelectronics Reliability 51 3 529 535 0026-2714 31 12 2011 2011-12-31 10.1016/j.microrel.2010.09.015 A £1M WAG KEF grant to Swansea generated many high impact papers subitted to RAE.These activities and publications triggered world-wide interest and Diodes ZETEX, one of the world’s largest semiconductor manufacturers and its engineers tested Swansea’s designed silicon chips and verified the findings. The cooperation with Diodes ZETEX and X-Fab led to an £1M Power System on Chip Development DTI grant (2006 - 2009). The industrial part of the DTI funded research was led by Prof Glenn Birchby, Chief Scientist at Diodes, and Dr Brendan Bold, Process Development Director, X-Fab Semiconductor Foundries. After the completion, the grant has been marked excellent by the TSB and achieved 95% of its targets. This paper reports on the outputs of the project. The LDMOS transistors designed by Swansea reduced the On-Resistance by more than half compared to X-Fab's previous design. They also extended the breakdwon voltage to more than 100V allowing modern LED lighting control designs to be introduced into CMOS. The papers reports how Dr Holland et al successfully transferred technology to a silicon foundry and is being used for high voltgae Power IC designs. COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2015-03-31T11:45:26.7084976 2013-09-03T06:20:05.0000000 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering P Holland 1 M Elwin 2 I Anteney 3 J Ellis 4 L Armstrong 5 G Birchby 6 P Igic 7 Paul Holland 8
title LDMOSFET with drain potential suppression for 100V Power IC technology
spellingShingle LDMOSFET with drain potential suppression for 100V Power IC technology
Paul Holland
title_short LDMOSFET with drain potential suppression for 100V Power IC technology
title_full LDMOSFET with drain potential suppression for 100V Power IC technology
title_fullStr LDMOSFET with drain potential suppression for 100V Power IC technology
title_full_unstemmed LDMOSFET with drain potential suppression for 100V Power IC technology
title_sort LDMOSFET with drain potential suppression for 100V Power IC technology
author_id_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f
author_id_fullname_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f_***_Paul Holland
author Paul Holland
author2 P Holland
M Elwin
I Anteney
J Ellis
L Armstrong
G Birchby
P Igic
Paul Holland
format Journal article
container_title Microelectronics Reliability
container_volume 51
container_issue 3
container_start_page 529
publishDate 2011
institution Swansea University
issn 0026-2714
doi_str_mv 10.1016/j.microrel.2010.09.015
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 0
active_str 0
published_date 2011-12-31T03:06:57Z
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score 11.013776

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