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A parallel implementation of sequential minimal optimization on FPGA

Daniel H. Noronha, Matheus Torquato Orcid Logo, Marcelo A.C. Fernandes

Microprocessors and Microsystems, Volume: 69, Pages: 138 - 151

Swansea University Author: Matheus Torquato Orcid Logo

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DOI (Published version): 10.1016/j.micpro.2019.06.007

Abstract

This paper proposes a parallel FPGA implementation of the training phase of a Support Vector Machine (SVM). The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO impl...

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Published in: Microprocessors and Microsystems
ISSN: 0141-9331
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa50890
first_indexed 2019-06-19T20:52:49Z
last_indexed 2019-07-03T20:53:42Z
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spelling 2019-07-03T15:38:16.7912354 v2 50890 2019-06-19 A parallel implementation of sequential minimal optimization on FPGA 7a053c668886b4642286baed36fdba90 0000-0001-6356-3538 Matheus Torquato Matheus Torquato true false 2019-06-19 MACS This paper proposes a parallel FPGA implementation of the training phase of a Support Vector Machine (SVM). The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO implementation is also highly parallel and uses some acceleration techniques, such as the error cache. Moreover, the Hardware Friendly Kernel (HFK) is used in order to reduce the kernel’s area, enabling an increase in the number of kernels per area. After the parallel implementation in hardware, the SVM is validated by bit-accurate simulation. Finally, analysis associated with the temporal performance of the proposed structure, as well as analysis associated with FPGAs area usage is performed. Journal Article Microprocessors and Microsystems 69 138 151 0141-9331 SVM, SMO, FPGA, Support vector machine, Sequential minimal optimization, Hardware 30 9 2019 2019-09-30 10.1016/j.micpro.2019.06.007 COLLEGE NANME Mathematics and Computer Science School COLLEGE CODE MACS Swansea University 2019-07-03T15:38:16.7912354 2019-06-19T16:32:59.2857807 Faculty of Science and Engineering School of Engineering and Applied Sciences - Uncategorised Daniel H. Noronha 1 Matheus Torquato 0000-0001-6356-3538 2 Marcelo A.C. Fernandes 3 0050890-24062019104021.pdf noronha2019.pdf 2019-06-24T10:40:21.1930000 Output 20066942 application/pdf Accepted Manuscript true 2020-06-13T00:00:00.0000000 true eng
title A parallel implementation of sequential minimal optimization on FPGA
spellingShingle A parallel implementation of sequential minimal optimization on FPGA
Matheus Torquato
title_short A parallel implementation of sequential minimal optimization on FPGA
title_full A parallel implementation of sequential minimal optimization on FPGA
title_fullStr A parallel implementation of sequential minimal optimization on FPGA
title_full_unstemmed A parallel implementation of sequential minimal optimization on FPGA
title_sort A parallel implementation of sequential minimal optimization on FPGA
author_id_str_mv 7a053c668886b4642286baed36fdba90
author_id_fullname_str_mv 7a053c668886b4642286baed36fdba90_***_Matheus Torquato
author Matheus Torquato
author2 Daniel H. Noronha
Matheus Torquato
Marcelo A.C. Fernandes
format Journal article
container_title Microprocessors and Microsystems
container_volume 69
container_start_page 138
publishDate 2019
institution Swansea University
issn 0141-9331
doi_str_mv 10.1016/j.micpro.2019.06.007
college_str Faculty of Science and Engineering
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hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Engineering and Applied Sciences - Uncategorised{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Engineering and Applied Sciences - Uncategorised
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description This paper proposes a parallel FPGA implementation of the training phase of a Support Vector Machine (SVM). The training phase of the SVM is implemented using Sequential Minimal Optimization (SMO), which enables the resolution of a complex convex optimization problem using simple steps. The SMO implementation is also highly parallel and uses some acceleration techniques, such as the error cache. Moreover, the Hardware Friendly Kernel (HFK) is used in order to reduce the kernel’s area, enabling an increase in the number of kernels per area. After the parallel implementation in hardware, the SVM is validated by bit-accurate simulation. Finally, analysis associated with the temporal performance of the proposed structure, as well as analysis associated with FPGAs area usage is performed.
published_date 2019-09-30T19:45:20Z
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score 11.04748

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