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Journal article 1179 views 272 downloads

Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters

Zhongfu Zhou Orcid Logo

Electric Power Components and Systems, Volume: 46, Issue: 14-15, Pages: 1662 - 10

Swansea University Author: Zhongfu Zhou Orcid Logo

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DOI (Published version): 10.1080/15325008.2018.1511640

Abstract

In this paper, a novel synchronous rotating-frame based phase-locked loop (PLL) for a single-phase PV inverter control system is presented. Detailed PLL mathematical model and the digital implementation for a single-phase PV inverter system are presented. A practical solution for transport delay bas...

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Published in: Electric Power Components and Systems
ISSN: 1532-5016 1532-5008
Published: USA Taylor & Francis 2018
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URI: https://cronfa.swan.ac.uk/Record/cronfa45963
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first_indexed 2018-11-18T20:18:33Z
last_indexed 2019-07-29T22:19:38Z
id cronfa45963
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spelling 2019-07-29T15:14:54.0536315 v2 45963 2018-11-18 Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters 614fc57cde2ee383718d4f4c462b5fba 0000-0002-0843-7253 Zhongfu Zhou Zhongfu Zhou true false 2018-11-18 EEEG In this paper, a novel synchronous rotating-frame based phase-locked loop (PLL) for a single-phase PV inverter control system is presented. Detailed PLL mathematical model and the digital implementation for a single-phase PV inverter system are presented. A practical solution for transport delay based orthogonal signal generation using first-in-first-out (FIFO) circular buffer is also discussed. Details of implementation for a real-time system using digital signal processor were also described. The performance of the developed PLL was experimentally validated on a developed single-phase PV inverter prototype Journal Article Electric Power Components and Systems 46 14-15 1662 10 Taylor & Francis USA 1532-5016 1532-5008 Single-phase PLL, orthogonal signal generator, PI controller, and single-phase PV inverter 24 12 2018 2018-12-24 10.1080/15325008.2018.1511640 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2019-07-29T15:14:54.0536315 2018-11-18T13:23:34.4562245 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Zhongfu Zhou 0000-0002-0843-7253 1 0045963-22012019161841.pdf zhou2018v2.pdf 2019-01-22T16:18:41.5330000 Output 887799 application/pdf Accepted Manuscript true 2019-12-24T00:00:00.0000000 true eng
title Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters
spellingShingle Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters
Zhongfu Zhou
title_short Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters
title_full Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters
title_fullStr Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters
title_full_unstemmed Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters
title_sort Design and Implementation of Digital Phase Locked Loop for Single-Phase Grid-Tied PV Inverters
author_id_str_mv 614fc57cde2ee383718d4f4c462b5fba
author_id_fullname_str_mv 614fc57cde2ee383718d4f4c462b5fba_***_Zhongfu Zhou
author Zhongfu Zhou
author2 Zhongfu Zhou
format Journal article
container_title Electric Power Components and Systems
container_volume 46
container_issue 14-15
container_start_page 1662
publishDate 2018
institution Swansea University
issn 1532-5016
1532-5008
doi_str_mv 10.1080/15325008.2018.1511640
publisher Taylor & Francis
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description In this paper, a novel synchronous rotating-frame based phase-locked loop (PLL) for a single-phase PV inverter control system is presented. Detailed PLL mathematical model and the digital implementation for a single-phase PV inverter system are presented. A practical solution for transport delay based orthogonal signal generation using first-in-first-out (FIFO) circular buffer is also discussed. Details of implementation for a real-time system using digital signal processor were also described. The performance of the developed PLL was experimentally validated on a developed single-phase PV inverter prototype
published_date 2018-12-24T03:57:39Z
_version_ 1763752918772613120
score 11.036553

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