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A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture

P.M Holland, M. P Elwin, S Batcup, Z Zhou, P. M Igic, Paul Holland

Microelectronics, 2008. MIEL 2008. 26th International Conference on, Pages: 177 - 179

Swansea University Author: Paul Holland

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DOI (Published version): 10.1109/ICMEL.2008.4559252

Published in: Microelectronics, 2008. MIEL 2008. 26th International Conference on
Published: 2008
URI: https://cronfa.swan.ac.uk/Record/cronfa5751
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spelling 2015-03-31T11:45:47.6428924 v2 5751 2013-09-03 A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture 9c7eea4ea9d615fcbf2801a672dd2e7f Paul Holland Paul Holland true false 2013-09-03 EEEG Conference Paper/Proceeding/Abstract Microelectronics, 2008. MIEL 2008. 26th International Conference on 177 179 31 12 2008 2008-12-31 10.1109/ICMEL.2008.4559252 A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture.This paper presents a novel approach to implement a high voltage transistor into a CMOS process and study the effects on circuit reliability. COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2015-03-31T11:45:47.6428924 2013-09-03T06:19:58.0000000 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering P.M Holland 1 M. P Elwin 2 S Batcup 3 Z Zhou 4 P. M Igic 5 Paul Holland 6
title A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
spellingShingle A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
Paul Holland
title_short A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
title_full A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
title_fullStr A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
title_full_unstemmed A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
title_sort A study of latch-up robustness for a new p-buffer CMOS based Power IC Technology architecture
author_id_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f
author_id_fullname_str_mv 9c7eea4ea9d615fcbf2801a672dd2e7f_***_Paul Holland
author Paul Holland
author2 P.M Holland
M. P Elwin
S Batcup
Z Zhou
P. M Igic
Paul Holland
format Conference Paper/Proceeding/Abstract
container_title Microelectronics, 2008. MIEL 2008. 26th International Conference on
container_start_page 177
publishDate 2008
institution Swansea University
doi_str_mv 10.1109/ICMEL.2008.4559252
college_str Faculty of Science and Engineering
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hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
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active_str 0
published_date 2008-12-31T03:06:57Z
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score 11.013619

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