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Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes

Daniel Nagy, Gabriel Espineira, Guillermo Indalecio, Antonio J. Garcia-Loureiro, Karol Kalna Orcid Logo, Natalia Seoane

IEEE Access, Volume: 8, Pages: 53196 - 53202

Swansea University Author: Karol Kalna Orcid Logo

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DOI (Published version): 10.1109/access.2020.2980925

Abstract

Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( LG ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based...

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Published in: IEEE Access
ISSN: 2169-3536
Published: Institute of Electrical and Electronics Engineers (IEEE) 2020
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URI: https://cronfa.swan.ac.uk/Record/cronfa53939
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first_indexed 2020-04-14T13:46:33Z
last_indexed 2021-08-07T03:10:42Z
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spelling 2021-08-06T10:06:35.7047709 v2 53939 2020-04-14 Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2020-04-14 EEEG Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( LG ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to LG of 16 nm offering a larger on-current ( ION ) and slightly better sub-threshold characteristics. Below LG of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( IOFF ), and the largest ION/IOFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body. Journal Article IEEE Access 8 53196 53202 Institute of Electrical and Electronics Engineers (IEEE) 2169-3536 26 3 2020 2020-03-26 10.1109/access.2020.2980925 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University Another institution paid the OA fee University of Santiago De Compostela 2021-08-06T10:06:35.7047709 2020-04-14T08:24:03.5458831 Professional Services ISS - Uncategorised Daniel Nagy 1 Gabriel Espineira 2 Guillermo Indalecio 3 Antonio J. Garcia-Loureiro 4 Karol Kalna 0000-0002-6333-9189 5 Natalia Seoane 6 53939__17053__639075c9775a4e0098bed8791269586c.pdf 53939.pdf 2020-04-14T08:27:21.1024337 Output 2303073 application/pdf Version of Record true This work is licensed under a Creative Commons Attribution 4.0 License. true eng https://creativecommons.org/licenses/by/4.0/
title Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
spellingShingle Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
Karol Kalna
title_short Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
title_full Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
title_fullStr Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
title_full_unstemmed Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
title_sort Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Karol Kalna
author2 Daniel Nagy
Gabriel Espineira
Guillermo Indalecio
Antonio J. Garcia-Loureiro
Karol Kalna
Natalia Seoane
format Journal article
container_title IEEE Access
container_volume 8
container_start_page 53196
publishDate 2020
institution Swansea University
issn 2169-3536
doi_str_mv 10.1109/access.2020.2980925
publisher Institute of Electrical and Electronics Engineers (IEEE)
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hierarchy_top_title Professional Services
hierarchy_parent_id professionalservices
hierarchy_parent_title Professional Services
department_str ISS - Uncategorised{{{_:::_}}}Professional Services{{{_:::_}}}ISS - Uncategorised
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description Nanosheet (NS) and nanowire (NW) FET architectures scaled to a gate length ( LG ) of 16 nm and below are benchmarked against equivalent FinFETs. The device performance is predicted using a 3D finite element drift-diffusion/Monte Carlo simulation toolbox with integrated 2D Schrödinger equation based quantum corrections. The NS FET is a viable replacement for the FinFET in high performance (HP) applications when scaled down to LG of 16 nm offering a larger on-current ( ION ) and slightly better sub-threshold characteristics. Below LG of 16 nm, the NW FET becomes the most promising architecture offering an almost ideal sub-threshold swing, the smallest off-current ( IOFF ), and the largest ION/IOFF ratio out of the three architectures. However, the NW FET suffers from early ION saturation with the increasing gate bias that can be tackled by minimizing interface roughness and/or by optimisation of a doping profile in the device body.
published_date 2020-03-26T04:07:11Z
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score 11.013641

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