Journal article 726 views 450 downloads
Parallel Implementation of Particle Swarm Optimization on FPGA
IEEE Transactions on Circuits and Systems II: Express Briefs, Volume: 66, Issue: 11, Pages: 1875 - 1879
Swansea University Author: Matheus Torquato
-
PDF | Accepted Manuscript
Download (907.61KB)
DOI (Published version): 10.1109/tcsii.2019.2895343
Abstract
This brief proposes a parallel implementation, with fixed point, of the particle swarm optimization (PSO) algorithm on field-programmable gate array (FPGA). Results associated with the processing time and area occupancy on FPGA for several numbers of particles and dimensions were analyzed. Studies c...
Published in: | IEEE Transactions on Circuits and Systems II: Express Briefs |
---|---|
ISSN: | 1549-7747 1558-3791 |
Published: |
Institute of Electrical and Electronics Engineers (IEEE)
2019
|
Online Access: |
Check full text
|
URI: | https://cronfa.swan.ac.uk/Record/cronfa52618 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
first_indexed |
2019-10-31T13:18:31Z |
---|---|
last_indexed |
2023-02-23T04:04:39Z |
id |
cronfa52618 |
recordtype |
SURis |
fullrecord |
<?xml version="1.0"?><rfc1807><datestamp>2023-02-22T15:52:05.8083145</datestamp><bib-version>v2</bib-version><id>52618</id><entry>2019-10-31</entry><title>Parallel Implementation of Particle Swarm Optimization on FPGA</title><swanseaauthors><author><sid>7a053c668886b4642286baed36fdba90</sid><ORCID>0000-0001-6356-3538</ORCID><firstname>Matheus</firstname><surname>Torquato</surname><name>Matheus Torquato</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2019-10-31</date><deptcode>SCS</deptcode><abstract>This brief proposes a parallel implementation, with fixed point, of the particle swarm optimization (PSO) algorithm on field-programmable gate array (FPGA). Results associated with the processing time and area occupancy on FPGA for several numbers of particles and dimensions were analyzed. Studies concerning the accuracy of the PSO response for the optimization problem using the Rastrigin function were also analyzed for the hardware implementation. The project was developed on the Virtex-6 xc6vcx240t 1ff1156 FPGA.</abstract><type>Journal Article</type><journal>IEEE Transactions on Circuits and Systems II: Express Briefs</journal><volume>66</volume><journalNumber>11</journalNumber><paginationStart>1875</paginationStart><paginationEnd>1879</paginationEnd><publisher>Institute of Electrical and Electronics Engineers (IEEE)</publisher><placeOfPublication/><isbnPrint/><isbnElectronic/><issnPrint>1549-7747</issnPrint><issnElectronic>1558-3791</issnElectronic><keywords/><publishedDay>1</publishedDay><publishedMonth>11</publishedMonth><publishedYear>2019</publishedYear><publishedDate>2019-11-01</publishedDate><doi>10.1109/tcsii.2019.2895343</doi><url/><notes/><college>COLLEGE NANME</college><department>Computer Science</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>SCS</DepartmentCode><institution>Swansea University</institution><apcterm/><funders/><projectreference/><lastEdited>2023-02-22T15:52:05.8083145</lastEdited><Created>2019-10-31T11:22:50.8753281</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Alexandre L. X. Da</firstname><surname>Costa</surname><order>1</order></author><author><firstname>Caroline A. D.</firstname><surname>Silva</surname><order>2</order></author><author><firstname>Matheus</firstname><surname>Torquato</surname><orcid>0000-0001-6356-3538</orcid><order>3</order></author><author><firstname>Marcelo A. C.</firstname><surname>Fernandes</surname><order>4</order></author></authors><documents><document><filename>52618__15758__2b7c86b92a784cb2934a6cc6b191183f.pdf</filename><originalFilename>decosta2019.pdf</originalFilename><uploaded>2019-10-31T11:26:54.2163500</uploaded><type>Output</type><contentLength>929388</contentLength><contentType>application/pdf</contentType><version>Accepted Manuscript</version><cronfaStatus>true</cronfaStatus><embargoDate>2019-10-31T00:00:00.0000000</embargoDate><copyrightCorrect>true</copyrightCorrect></document></documents><OutputDurs/></rfc1807> |
spelling |
2023-02-22T15:52:05.8083145 v2 52618 2019-10-31 Parallel Implementation of Particle Swarm Optimization on FPGA 7a053c668886b4642286baed36fdba90 0000-0001-6356-3538 Matheus Torquato Matheus Torquato true false 2019-10-31 SCS This brief proposes a parallel implementation, with fixed point, of the particle swarm optimization (PSO) algorithm on field-programmable gate array (FPGA). Results associated with the processing time and area occupancy on FPGA for several numbers of particles and dimensions were analyzed. Studies concerning the accuracy of the PSO response for the optimization problem using the Rastrigin function were also analyzed for the hardware implementation. The project was developed on the Virtex-6 xc6vcx240t 1ff1156 FPGA. Journal Article IEEE Transactions on Circuits and Systems II: Express Briefs 66 11 1875 1879 Institute of Electrical and Electronics Engineers (IEEE) 1549-7747 1558-3791 1 11 2019 2019-11-01 10.1109/tcsii.2019.2895343 COLLEGE NANME Computer Science COLLEGE CODE SCS Swansea University 2023-02-22T15:52:05.8083145 2019-10-31T11:22:50.8753281 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Alexandre L. X. Da Costa 1 Caroline A. D. Silva 2 Matheus Torquato 0000-0001-6356-3538 3 Marcelo A. C. Fernandes 4 52618__15758__2b7c86b92a784cb2934a6cc6b191183f.pdf decosta2019.pdf 2019-10-31T11:26:54.2163500 Output 929388 application/pdf Accepted Manuscript true 2019-10-31T00:00:00.0000000 true |
title |
Parallel Implementation of Particle Swarm Optimization on FPGA |
spellingShingle |
Parallel Implementation of Particle Swarm Optimization on FPGA Matheus Torquato |
title_short |
Parallel Implementation of Particle Swarm Optimization on FPGA |
title_full |
Parallel Implementation of Particle Swarm Optimization on FPGA |
title_fullStr |
Parallel Implementation of Particle Swarm Optimization on FPGA |
title_full_unstemmed |
Parallel Implementation of Particle Swarm Optimization on FPGA |
title_sort |
Parallel Implementation of Particle Swarm Optimization on FPGA |
author_id_str_mv |
7a053c668886b4642286baed36fdba90 |
author_id_fullname_str_mv |
7a053c668886b4642286baed36fdba90_***_Matheus Torquato |
author |
Matheus Torquato |
author2 |
Alexandre L. X. Da Costa Caroline A. D. Silva Matheus Torquato Marcelo A. C. Fernandes |
format |
Journal article |
container_title |
IEEE Transactions on Circuits and Systems II: Express Briefs |
container_volume |
66 |
container_issue |
11 |
container_start_page |
1875 |
publishDate |
2019 |
institution |
Swansea University |
issn |
1549-7747 1558-3791 |
doi_str_mv |
10.1109/tcsii.2019.2895343 |
publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
college_str |
Faculty of Science and Engineering |
hierarchytype |
|
hierarchy_top_id |
facultyofscienceandengineering |
hierarchy_top_title |
Faculty of Science and Engineering |
hierarchy_parent_id |
facultyofscienceandengineering |
hierarchy_parent_title |
Faculty of Science and Engineering |
department_str |
School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering |
document_store_str |
1 |
active_str |
0 |
description |
This brief proposes a parallel implementation, with fixed point, of the particle swarm optimization (PSO) algorithm on field-programmable gate array (FPGA). Results associated with the processing time and area occupancy on FPGA for several numbers of particles and dimensions were analyzed. Studies concerning the accuracy of the PSO response for the optimization problem using the Rastrigin function were also analyzed for the hardware implementation. The project was developed on the Virtex-6 xc6vcx240t 1ff1156 FPGA. |
published_date |
2019-11-01T04:05:05Z |
_version_ |
1763753386871619584 |
score |
11.037319 |