No Cover Image

Journal article 1080 views 113 downloads

A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs

Natalia Seoane, Daniel Nagy, Guillermo Indalecio, Gabriel Espiñeira, Karol Kalna Orcid Logo, Antonio García-Loureiro

Materials, Volume: 12, Issue: 15, Start page: 2391

Swansea University Author: Karol Kalna Orcid Logo

  • seoane2019(4).pdf

    PDF | Version of Record

    Distributed under the terms of a Creative Commons Attribution (CC-BY-4.0)

    Download (2.14MB)

Check full text

DOI (Published version): 10.3390/ma12152391

Abstract

An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effec...

Full description

Published in: Materials
ISSN: 1996-1944
Published: 2019
Online Access: Check full text

URI: https://cronfa.swan.ac.uk/Record/cronfa51467
Tags: Add Tag
No Tags, Be the first to tag this record!
first_indexed 2019-08-19T15:29:39Z
last_indexed 2019-08-27T15:30:37Z
id cronfa51467
recordtype SURis
fullrecord <?xml version="1.0"?><rfc1807><datestamp>2019-08-27T12:38:12.4980898</datestamp><bib-version>v2</bib-version><id>51467</id><entry>2019-08-19</entry><title>A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs</title><swanseaauthors><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2019-08-19</date><deptcode>EEEG</deptcode><abstract>An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current ( IOFF ) of 0.03 &#x3BC; A/ &#x3BC; m, and an on-current ( ION ) of 1770 &#x3BC; A/ &#x3BC; m, with the ION/IOFF ratio 6.63&#xD7;104 , a value 27% larger than that of a 10.7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55.5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.</abstract><type>Journal Article</type><journal>Materials</journal><volume>12</volume><journalNumber>15</journalNumber><paginationStart>2391</paginationStart><publisher/><issnElectronic>1996-1944</issnElectronic><keywords>nanowire field-effect transistors; variability effects; Monte Carlo; Schr&#xF6;dinger based quantum corrections; drift-diffusion</keywords><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2019</publishedYear><publishedDate>2019-12-31</publishedDate><doi>10.3390/ma12152391</doi><url/><notes/><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2019-08-27T12:38:12.4980898</lastEdited><Created>2019-08-19T10:12:45.6161618</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>Natalia</firstname><surname>Seoane</surname><order>1</order></author><author><firstname>Daniel</firstname><surname>Nagy</surname><order>2</order></author><author><firstname>Guillermo</firstname><surname>Indalecio</surname><order>3</order></author><author><firstname>Gabriel</firstname><surname>Espi&#xF1;eira</surname><order>4</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>5</order></author><author><firstname>Antonio</firstname><surname>Garc&#xED;a-Loureiro</surname><order>6</order></author></authors><documents><document><filename>0051467-19082019101502.pdf</filename><originalFilename>seoane2019(4).pdf</originalFilename><uploaded>2019-08-19T10:15:02.9470000</uploaded><type>Output</type><contentLength>2245503</contentLength><contentType>application/pdf</contentType><version>Version of Record</version><cronfaStatus>true</cronfaStatus><embargoDate>2019-08-19T00:00:00.0000000</embargoDate><documentNotes>Distributed under the terms of a Creative Commons Attribution (CC-BY-4.0)</documentNotes><copyrightCorrect>true</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807>
spelling 2019-08-27T12:38:12.4980898 v2 51467 2019-08-19 A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2019-08-19 EEEG An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current ( IOFF ) of 0.03 μ A/ μ m, and an on-current ( ION ) of 1770 μ A/ μ m, with the ION/IOFF ratio 6.63×104 , a value 27% larger than that of a 10.7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55.5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction. Journal Article Materials 12 15 2391 1996-1944 nanowire field-effect transistors; variability effects; Monte Carlo; Schrödinger based quantum corrections; drift-diffusion 31 12 2019 2019-12-31 10.3390/ma12152391 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2019-08-27T12:38:12.4980898 2019-08-19T10:12:45.6161618 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Natalia Seoane 1 Daniel Nagy 2 Guillermo Indalecio 3 Gabriel Espiñeira 4 Karol Kalna 0000-0002-6333-9189 5 Antonio García-Loureiro 6 0051467-19082019101502.pdf seoane2019(4).pdf 2019-08-19T10:15:02.9470000 Output 2245503 application/pdf Version of Record true 2019-08-19T00:00:00.0000000 Distributed under the terms of a Creative Commons Attribution (CC-BY-4.0) true eng
title A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
spellingShingle A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
Karol Kalna
title_short A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
title_full A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
title_fullStr A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
title_full_unstemmed A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
title_sort A Multi-Method Simulation Toolbox to Study Performance and Variability of Nanowire FETs
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Karol Kalna
author2 Natalia Seoane
Daniel Nagy
Guillermo Indalecio
Gabriel Espiñeira
Karol Kalna
Antonio García-Loureiro
format Journal article
container_title Materials
container_volume 12
container_issue 15
container_start_page 2391
publishDate 2019
institution Swansea University
issn 1996-1944
doi_str_mv 10.3390/ma12152391
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
active_str 0
description An in-house-built three-dimensional multi-method semi-classical/classical toolbox has been developed to characterise the performance, scalability, and variability of state-of-the-art semiconductor devices. To demonstrate capabilities of the toolbox, a 10 nm gate length Si gate-all-around field-effect transistor is selected as a benchmark device. The device exhibits an off-current ( IOFF ) of 0.03 μ A/ μ m, and an on-current ( ION ) of 1770 μ A/ μ m, with the ION/IOFF ratio 6.63×104 , a value 27% larger than that of a 10.7 nm gate length Si FinFET. The device SS is 71 mV/dec, no far from the ideal limit of 60 mV/dec. The threshold voltage standard deviation due to statistical combination of four sources of variability (line- and gate-edge roughness, metal grain granularity, and random dopants) is 55.5 mV, a value noticeably larger than that of the equivalent FinFET (30 mV). Finally, using a fluctuation sensitivity map, we establish which regions of the device are the most sensitive to the line-edge roughness and the metal grain granularity variability effects. The on-current of the device is strongly affected by any line-edge roughness taking place near the source-gate junction or by metal grains localised between the middle of the gate and the proximity of the gate-source junction.
published_date 2019-12-31T04:03:22Z
_version_ 1763753278371266560
score 11.037603