Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures

Mohamed, Alnazer

doi:10.23889/Suthesis.51283

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Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures / Alnazer Mohamed

Swansea University Author: Alnazer Mohamed

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DOI (Published version): 10.23889/Suthesis.51283

Abstract

In this thesis, a multi-scale simulation study of Ni/InAs nano-scale contact aimed for the sub-14 nm technology is carried out to understand material and transport properties at a metal-semiconductor interface. The deposited Ni metal contact on an 11 nm thick InAs channel forms an 8.5 nm thick InAs...

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Published:	2019
Institution:	Swansea University
Degree level:	Doctoral
Degree name:	Ph.D
URI:	https://cronfa.swan.ac.uk/Record/cronfa51283

first_indexed	2019-07-31T22:30:21Z
last_indexed	2025-03-20T07:28:11Z
id	cronfa51283
recordtype	RisThesis
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The density func-tional theory (DFT) calculations reveal a band gap narrowing in the InAs at the metal-semiconductor interface. The one-dimensional (1D) self-consistent Poisson-Schr¨odinger transport simulations using real-space material parameters extracted from the DFT calculations at the metal-semiconductor interface, exhibiting band gap narrowing, give a speciﬁc sheet resistance of Rsh = 90.9 Ω/sq which is in a good agreement with an experimental value of 97 Ω/sq.In this thesis, ZnO thin-ﬁlm transistors (TFTs) with diﬀerent channel lengths (10 µm, 5 µm, 4 µm, and 2 µm) have been characterised. The current-voltage measurements indicate n-type channel, enhancement mode TFT operation with an excellent drain current saturation. A transmission line method (TLM) is employed to extract the contact resistance, eﬀective and channel electron mobility from current-voltage char-acteristics in the linear regime of transistor operation. Contact resistance and both eﬀective and channel electron mobility exhibit a dependency on the channel length as a function of gate bias (10 V and 15 V). The extracted channel electron mobility is high as 0.782 cm2/Vs and 0.83 cm2/Vs (increase by 6 %) at gate biases of 10 V and 15 V, respectively, for the 10 µm channel length as compared to eﬀective mo-bility of 0.11 cm2/Vs and 0.38 cm2/Vs, at the same respective biases.The channel mobility increases from 8.9 cm2/Vs to 19.04 cm2/Vs (increase by 115 %) when gate biases increases from 10 V and 15 V, respectively, when the channel length is scaled down to 2 µm. The increase of the electron channel mobility during the channel scaling is indicative of a reduced electron scattering due to the increase in electric ﬁeld along the channel. This reduction in the carrier scattering increases electron velocity because electrons will have a longer mean-free path in the scaled thin-ﬁlm channels. These values indicate a substantial increase in ZnO TFTs elec-tron mobility as compared to previously reported values for such devices.In addition, ZnO NWs ﬁeld-eﬀect transistors (NWs-FETs) fabricated by using top-down fabrication have been studied. The top-down fabrication method starts with a thin ﬁlm deposition by remote plasma enhanced ALD (PEALD). The PEALD is followed by aniso-tropically reactive ion etch (RIE) to produce ZnO NWs with diﬀerent channel lengths (20 µm, 10 µm, and 2 µm). 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spelling	2025-03-19T12:20:42.2986846 v2 51283 2019-07-31 Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures c394c8e21e8b61ac5798f055b98bae1f NULL Alnazer Mohamed Alnazer Mohamed true true 2019-07-31 In this thesis, a multi-scale simulation study of Ni/InAs nano-scale contact aimed for the sub-14 nm technology is carried out to understand material and transport properties at a metal-semiconductor interface. The deposited Ni metal contact on an 11 nm thick InAs channel forms an 8.5 nm thick InAs leaving a 2.5 nm thick InAs channel on a p-type doped (1×1016 cm−3) AlAs0.47Sb0.53 buﬀer. The density func-tional theory (DFT) calculations reveal a band gap narrowing in the InAs at the metal-semiconductor interface. The one-dimensional (1D) self-consistent Poisson-Schr¨odinger transport simulations using real-space material parameters extracted from the DFT calculations at the metal-semiconductor interface, exhibiting band gap narrowing, give a speciﬁc sheet resistance of Rsh = 90.9 Ω/sq which is in a good agreement with an experimental value of 97 Ω/sq.In this thesis, ZnO thin-ﬁlm transistors (TFTs) with diﬀerent channel lengths (10 µm, 5 µm, 4 µm, and 2 µm) have been characterised. The current-voltage measurements indicate n-type channel, enhancement mode TFT operation with an excellent drain current saturation. A transmission line method (TLM) is employed to extract the contact resistance, eﬀective and channel electron mobility from current-voltage char-acteristics in the linear regime of transistor operation. Contact resistance and both eﬀective and channel electron mobility exhibit a dependency on the channel length as a function of gate bias (10 V and 15 V). The extracted channel electron mobility is high as 0.782 cm2/Vs and 0.83 cm2/Vs (increase by 6 %) at gate biases of 10 V and 15 V, respectively, for the 10 µm channel length as compared to eﬀective mo-bility of 0.11 cm2/Vs and 0.38 cm2/Vs, at the same respective biases.The channel mobility increases from 8.9 cm2/Vs to 19.04 cm2/Vs (increase by 115 %) when gate biases increases from 10 V and 15 V, respectively, when the channel length is scaled down to 2 µm. The increase of the electron channel mobility during the channel scaling is indicative of a reduced electron scattering due to the increase in electric ﬁeld along the channel. This reduction in the carrier scattering increases electron velocity because electrons will have a longer mean-free path in the scaled thin-ﬁlm channels. These values indicate a substantial increase in ZnO TFTs elec-tron mobility as compared to previously reported values for such devices.In addition, ZnO NWs ﬁeld-eﬀect transistors (NWs-FETs) fabricated by using top-down fabrication have been studied. The top-down fabrication method starts with a thin ﬁlm deposition by remote plasma enhanced ALD (PEALD). The PEALD is followed by aniso-tropically reactive ion etch (RIE) to produce ZnO NWs with diﬀerent channel lengths (20 µm, 10 µm, and 2 µm). Optical and electrical charac-terisations are carried out to study the impact of scaling channel length (Lch) in the transistors. E-Thesis Interfaces, Junctions, Nanoscale, ZnO, InAs, Transistor Metals, semiconductors, Contacts 31 12 2019 2019-12-31 10.23889/Suthesis.51283 COLLEGE NANME Engineering COLLEGE CODE Swansea University Doctoral Ph.D 2025-03-19T12:20:42.2986846 2019-07-31T15:31:26.7576413 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering Alnazer Mohamed NULL 1 0051283-31072019160924.pdf Mohamed_Alnazer_PhD_Thesis_Final.pdf 2019-07-31T16:09:24.1430000 Output 21094038 application/pdf E-Thesis – open access true 2022-07-20T00:00:00.0000000 true
title	Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures
spellingShingle	Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures Alnazer Mohamed
title_short	Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures
title_full	Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures
title_fullStr	Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures
title_full_unstemmed	Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures
title_sort	Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures
author_id_str_mv	c394c8e21e8b61ac5798f055b98bae1f
author_id_fullname_str_mv	c394c8e21e8b61ac5798f055b98bae1f_***_Alnazer Mohamed
author	Alnazer Mohamed
author2	Alnazer Mohamed
format	E-Thesis
publishDate	2019
institution	Swansea University
doi_str_mv	10.23889/Suthesis.51283
college_str	Faculty of Science and Engineering
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hierarchy_top_id	facultyofscienceandengineering
hierarchy_top_title	Faculty of Science and Engineering
hierarchy_parent_id	facultyofscienceandengineering
hierarchy_parent_title	Faculty of Science and Engineering
department_str	School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
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description	In this thesis, a multi-scale simulation study of Ni/InAs nano-scale contact aimed for the sub-14 nm technology is carried out to understand material and transport properties at a metal-semiconductor interface. The deposited Ni metal contact on an 11 nm thick InAs channel forms an 8.5 nm thick InAs leaving a 2.5 nm thick InAs channel on a p-type doped (1×1016 cm−3) AlAs0.47Sb0.53 buﬀer. The density func-tional theory (DFT) calculations reveal a band gap narrowing in the InAs at the metal-semiconductor interface. The one-dimensional (1D) self-consistent Poisson-Schr¨odinger transport simulations using real-space material parameters extracted from the DFT calculations at the metal-semiconductor interface, exhibiting band gap narrowing, give a speciﬁc sheet resistance of Rsh = 90.9 Ω/sq which is in a good agreement with an experimental value of 97 Ω/sq.In this thesis, ZnO thin-ﬁlm transistors (TFTs) with diﬀerent channel lengths (10 µm, 5 µm, 4 µm, and 2 µm) have been characterised. The current-voltage measurements indicate n-type channel, enhancement mode TFT operation with an excellent drain current saturation. A transmission line method (TLM) is employed to extract the contact resistance, eﬀective and channel electron mobility from current-voltage char-acteristics in the linear regime of transistor operation. Contact resistance and both eﬀective and channel electron mobility exhibit a dependency on the channel length as a function of gate bias (10 V and 15 V). The extracted channel electron mobility is high as 0.782 cm2/Vs and 0.83 cm2/Vs (increase by 6 %) at gate biases of 10 V and 15 V, respectively, for the 10 µm channel length as compared to eﬀective mo-bility of 0.11 cm2/Vs and 0.38 cm2/Vs, at the same respective biases.The channel mobility increases from 8.9 cm2/Vs to 19.04 cm2/Vs (increase by 115 %) when gate biases increases from 10 V and 15 V, respectively, when the channel length is scaled down to 2 µm. The increase of the electron channel mobility during the channel scaling is indicative of a reduced electron scattering due to the increase in electric ﬁeld along the channel. This reduction in the carrier scattering increases electron velocity because electrons will have a longer mean-free path in the scaled thin-ﬁlm channels. These values indicate a substantial increase in ZnO TFTs elec-tron mobility as compared to previously reported values for such devices.In addition, ZnO NWs ﬁeld-eﬀect transistors (NWs-FETs) fabricated by using top-down fabrication have been studied. The top-down fabrication method starts with a thin ﬁlm deposition by remote plasma enhanced ALD (PEALD). The PEALD is followed by aniso-tropically reactive ion etch (RIE) to produce ZnO NWs with diﬀerent channel lengths (20 µm, 10 µm, and 2 µm). Optical and electrical charac-terisations are carried out to study the impact of scaling channel length (Lch) in the transistors.
published_date	2019-12-31T07:35:18Z
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score	11.058973

Interfaces and Junctions in Nanoscale ZnO and InAs Transistor Structures / Alnazer Mohamed

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