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Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects

A Islam, K Kalna, Karol Kalna Orcid Logo

IOP Conference Series: Materials Science and Engineering, Volume: 504, Start page: 012021

Swansea University Author: Karol Kalna Orcid Logo

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DOI (Published version): 10.1088/1757-899X/504/1/012021

Abstract

The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor chann...

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Published in: IOP Conference Series: Materials Science and Engineering
ISSN: 1757-899X
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa50487
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first_indexed 2019-05-22T15:49:12Z
last_indexed 2019-07-18T21:35:36Z
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fullrecord <?xml version="1.0"?><rfc1807><datestamp>2019-07-18T15:41:26.1048434</datestamp><bib-version>v2</bib-version><id>50487</id><entry>2019-05-22</entry><title>Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects</title><swanseaauthors><author><sid>1329a42020e44fdd13de2f20d5143253</sid><ORCID>0000-0002-6333-9189</ORCID><firstname>Karol</firstname><surname>Kalna</surname><name>Karol Kalna</name><active>true</active><ethesisStudent>false</ethesisStudent></author></swanseaauthors><date>2019-05-22</date><deptcode>EEEG</deptcode><abstract>The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schr&#xF6;dinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schr&#xF6;dinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schr&#xF6;dinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages.</abstract><type>Journal Article</type><journal>IOP Conference Series: Materials Science and Engineering</journal><volume>504</volume><paginationStart>012021</paginationStart><publisher/><issnElectronic>1757-899X</issnElectronic><keywords/><publishedDay>31</publishedDay><publishedMonth>12</publishedMonth><publishedYear>2019</publishedYear><publishedDate>2019-12-31</publishedDate><doi>10.1088/1757-899X/504/1/012021</doi><url/><notes/><college>COLLEGE NANME</college><department>Electronic and Electrical Engineering</department><CollegeCode>COLLEGE CODE</CollegeCode><DepartmentCode>EEEG</DepartmentCode><institution>Swansea University</institution><apcterm/><lastEdited>2019-07-18T15:41:26.1048434</lastEdited><Created>2019-05-22T13:55:58.1111567</Created><path><level id="1">Faculty of Science and Engineering</level><level id="2">School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering</level></path><authors><author><firstname>A</firstname><surname>Islam</surname><order>1</order></author><author><firstname>K</firstname><surname>Kalna</surname><order>2</order></author><author><firstname>Karol</firstname><surname>Kalna</surname><orcid>0000-0002-6333-9189</orcid><order>3</order></author></authors><documents><document><filename>0050487-22052019135743.pdf</filename><originalFilename>islam2019.pdf</originalFilename><uploaded>2019-05-22T13:57:43.9900000</uploaded><type>Output</type><contentLength>4122709</contentLength><contentType>application/pdf</contentType><version>Version of Record</version><cronfaStatus>true</cronfaStatus><embargoDate>2019-05-22T00:00:00.0000000</embargoDate><documentNotes>Distributed under the terms of a Creative Commons Attribution Non-Commercial (CC-BY-3.0)</documentNotes><copyrightCorrect>true</copyrightCorrect><language>eng</language></document></documents><OutputDurs/></rfc1807>
spelling 2019-07-18T15:41:26.1048434 v2 50487 2019-05-22 Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects 1329a42020e44fdd13de2f20d5143253 0000-0002-6333-9189 Karol Kalna Karol Kalna true false 2019-05-22 EEEG The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schrödinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schrödinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schrödinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages. Journal Article IOP Conference Series: Materials Science and Engineering 504 012021 1757-899X 31 12 2019 2019-12-31 10.1088/1757-899X/504/1/012021 COLLEGE NANME Electronic and Electrical Engineering COLLEGE CODE EEEG Swansea University 2019-07-18T15:41:26.1048434 2019-05-22T13:55:58.1111567 Faculty of Science and Engineering School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering A Islam 1 K Kalna 2 Karol Kalna 0000-0002-6333-9189 3 0050487-22052019135743.pdf islam2019.pdf 2019-05-22T13:57:43.9900000 Output 4122709 application/pdf Version of Record true 2019-05-22T00:00:00.0000000 Distributed under the terms of a Creative Commons Attribution Non-Commercial (CC-BY-3.0) true eng
title Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects
spellingShingle Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects
Karol Kalna
title_short Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects
title_full Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects
title_fullStr Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects
title_full_unstemmed Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects
title_sort Analysis of electron transport in the nano-scaled Si, SOI and III-V MOSFETs: Si/SiO2 interface charges and quantum mechanical effects
author_id_str_mv 1329a42020e44fdd13de2f20d5143253
author_id_fullname_str_mv 1329a42020e44fdd13de2f20d5143253_***_Karol Kalna
author Karol Kalna
author2 A Islam
K Kalna
Karol Kalna
format Journal article
container_title IOP Conference Series: Materials Science and Engineering
container_volume 504
container_start_page 012021
publishDate 2019
institution Swansea University
issn 1757-899X
doi_str_mv 10.1088/1757-899X/504/1/012021
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Aerospace, Civil, Electrical, General and Mechanical Engineering - Electronic and Electrical Engineering
document_store_str 1
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description The ITRS predicts that the scaling of planar CMOS (Complementary Metal Oxide Semiconductor) technology will continue till the 22 nm technology node [1] and a possible extension beyond is appealing [2]. In this work, we investigate the effect of electron confinement [3] in nanoscaled transistor channels of 25 nm surface channel Si and 32 nm SOI (Silicon on Insulator) and 15 nm IF (Implant Free) III-V MOSFETs using a self-consistent solution of 1 D Poisson - Schrödinger equation [4,5]. For simulat ion and development with accuracy of nano-scaled of 25 nm gate length Si MOSFET (Metal Oxide Semiconductor Field Effect Transistor), 32 nm SOI Implant Free (IF) MOSFET, and 15nm Implant Free III-V MOSFET transistors, we investigated the bandstructure and quantum confinement effects occurring near the oxide-semiconductor interface inmetal-Oxide-Semiconductor (MOS) structure of Si MOSFET device. These investigation have been carried out using a selfconsistent solution of 1D Poisson-Schrödinger equation across the channel of conventional Si / SOI / III-V MOSFET Transistors. To solve self-consistently 1D Poisson-Schrödinger equations across the channel of a conventional Si, SOI, and an Implant Free III-V MOSFETs to determine the conduction and valence band profiles, electron density, electron sheet density, eigenstate and eigenfunctions in these structures. We present the simulat ion results of conduction band profile, electron density (classical and quantum mechanical), eigenstate and eigenfunctions for Si, SOI and III-V MOSFET structures at two different bias voltages of 0.5 V and 1.0 V. For comparison, we calculate the electron sheet density (quantum mechanically) as a function of the applied gate voltages.
published_date 2019-12-31T04:01:58Z
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