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Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder

Maria G. F. Coutinho, Matheus Torquato Orcid Logo, Marcelo A. C. Fernandes

IEEE Access, Pages: 1 - 1

Swansea University Author: Matheus Torquato Orcid Logo

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DOI (Published version): 10.1109/ACCESS.2019.2907261

Abstract

Deep learning techniques have been gaining prominence in the research world in the past years, however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodolog...

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Published in: IEEE Access
ISSN: 2169-3536
Published: 2019
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URI: https://cronfa.swan.ac.uk/Record/cronfa49874
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first_indexed 2019-04-04T16:40:50Z
last_indexed 2019-07-17T15:33:43Z
id cronfa49874
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spelling 2019-07-17T09:51:27.6797438 v2 49874 2019-04-03 Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder 7a053c668886b4642286baed36fdba90 0000-0001-6356-3538 Matheus Torquato Matheus Torquato true false 2019-04-03 SCS Deep learning techniques have been gaining prominence in the research world in the past years, however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodologies focusing on accelerating complex algorithms including those based on reconfigurable hardware has been showing significant results. Therefore, the objective of this work is to propose a neural network hardware implementation to be used in deep learning applications. The implementation was developed on a Field Programmable Gate Array (FPGA) and supports Deep Neural Network (DNN) trained with the Stacked Sparse Autoencoder (SSAE) technique. In order to allow DNNs with several inputs and layers on the FPGA, the systolic array technique was used in the entire architecture. Details regarding the designed implementation were evidenced, as well as the hardware area occupation in and the processing time for two different implementations. The results showed that both implementations achieved high throughput enabling Deep Learning techniques to be applied for problems with large data amounts. Journal Article IEEE Access 1 1 2169-3536 31 12 2019 2019-12-31 10.1109/ACCESS.2019.2907261 COLLEGE NANME Computer Science COLLEGE CODE SCS Swansea University 2019-07-17T09:51:27.6797438 2019-04-03T11:14:25.0904999 Faculty of Science and Engineering School of Engineering and Applied Sciences - Uncategorised Maria G. F. Coutinho 1 Matheus Torquato 0000-0001-6356-3538 2 Marcelo A. C. Fernandes 3 0049874-03042019111711.pdf coutinho2019v2.pdf 2019-04-03T11:17:11.6730000 Output 9766741 application/pdf Version of Record true 2019-04-03T00:00:00.0000000 true eng
title Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
spellingShingle Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
Matheus Torquato
title_short Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
title_full Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
title_fullStr Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
title_full_unstemmed Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
title_sort Deep Neural Network Hardware Implementation Based on Stacked Sparse Autoencoder
author_id_str_mv 7a053c668886b4642286baed36fdba90
author_id_fullname_str_mv 7a053c668886b4642286baed36fdba90_***_Matheus Torquato
author Matheus Torquato
author2 Maria G. F. Coutinho
Matheus Torquato
Marcelo A. C. Fernandes
format Journal article
container_title IEEE Access
container_start_page 1
publishDate 2019
institution Swansea University
issn 2169-3536
doi_str_mv 10.1109/ACCESS.2019.2907261
college_str Faculty of Science and Engineering
hierarchytype
hierarchy_top_id facultyofscienceandengineering
hierarchy_top_title Faculty of Science and Engineering
hierarchy_parent_id facultyofscienceandengineering
hierarchy_parent_title Faculty of Science and Engineering
department_str School of Engineering and Applied Sciences - Uncategorised{{{_:::_}}}Faculty of Science and Engineering{{{_:::_}}}School of Engineering and Applied Sciences - Uncategorised
document_store_str 1
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description Deep learning techniques have been gaining prominence in the research world in the past years, however, the deep learning algorithms have high computational cost, making them hard to be used to several commercial applications. On the other hand, new alternatives have been studied and some methodologies focusing on accelerating complex algorithms including those based on reconfigurable hardware has been showing significant results. Therefore, the objective of this work is to propose a neural network hardware implementation to be used in deep learning applications. The implementation was developed on a Field Programmable Gate Array (FPGA) and supports Deep Neural Network (DNN) trained with the Stacked Sparse Autoencoder (SSAE) technique. In order to allow DNNs with several inputs and layers on the FPGA, the systolic array technique was used in the entire architecture. Details regarding the designed implementation were evidenced, as well as the hardware area occupation in and the processing time for two different implementations. The results showed that both implementations achieved high throughput enabling Deep Learning techniques to be applied for problems with large data amounts.
published_date 2019-12-31T04:01:07Z
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score 11.037166

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